wkong_zhu
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I want use delay chain to deglitch input signal. for example.
--------------------------------------
module ( input I, output O)
wire [9:0] delay_net; /* synthesis syn_keep = 1*/
BUF delaybuffer[9:0] ( .I({delay_net[8:0], I}), .O(delay_net[9:0]) );
assign O = delay_net[9];
endmodule
----------------------------------
But after synplify_pro synthesis, The BUFs disappeared totoally. only assign statements left.
How should I keep combinational Delays after Synthesis and APR.
Anybody help me.
- - - Updated - - -
I use LUT4 to act like a delay cell, It also failed.
the 'syn_keep' can only keep net name, it can not keep LUT.
--------------------------------------
module ( input I, output O)
wire [9:0] delay_net; /* synthesis syn_keep = 1*/
BUF delaybuffer[9:0] ( .I({delay_net[8:0], I}), .O(delay_net[9:0]) );
assign O = delay_net[9];
endmodule
----------------------------------
But after synplify_pro synthesis, The BUFs disappeared totoally. only assign statements left.
How should I keep combinational Delays after Synthesis and APR.
Anybody help me.
- - - Updated - - -
I use LUT4 to act like a delay cell, It also failed.
the 'syn_keep' can only keep net name, it can not keep LUT.