How realize low timebase of oscilloscope in high speed ADC?

[alphi]

I design a home oscilloscope,use high speed ADC chip--ADC08100,AD sample rate of ADC08100 is 100MHz/s~20MHz/s. Now my oscilloscope need low timebase(such as 100KHz/s sample rate),i can not directly use 100KHz clock for ADC08100,so i use 20MHz for ADC08100,then use 100KHz for sram address counter.but it is not syncronize betwwen 100KHz clock and 20Mhz clock!
How can i to solute this question? anyone can help me,thank you!

 

[stroma]

Re: How realize low timebase of oscilloscope in high speed A

Hi alphi,
Why don’t you use a D flip-flop for synchronization? Connect unsync 100Khz to D input, synchronization clock /20 MHz/ to clock input and get synchronized 100 KHz clock from Q output.

 

[alphi]

Re: How realize low timebase of oscilloscope in high speed A

“use a D flip-flop for synchronization”，it can reduce metastability,but it can not completely eliminate metastability.it will generate some error data,even the error rate is very low.

 

[Beowolf]

Do you have on AD converion_complete pin? Use it to start clocking out 8 clocks @20MHz, then halt until next data is available...

 

[fobyellow]

The delay is caused by Propagation-Delay of the Freq-Devider, how about let the 20MHz clock pass through the same device to produce a same delay?