How power plane acts as a path for the return currents.

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In some pcb stackup's I can see that the power plane is given as reference to signal layers.

I have some questions regarding this.

1) May I know in that case how the return current flows.

2) Assume all my signals present in the layer belongs to 1.8V and I am proving a 3.3V power plane as reference. Will it cause any SI issues.

Below is an example of a stackup where power plane is given as reference to bottom signal layer.This is just for a refrence

 

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Current flows around a conducting loop. The loop could be made
of a skinny wire or a fat slab, still it exists and conducts. The
qualities, those vary with material and geometry.

In a 2D universe a plane is the best you can do (varying thickness
over a small range, still looking ideal-plane-ish).

But current could return (with slightly higher voltage loss) whether
it's a plane or some other shape.
 

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The answer depends in part on information you are not giving.
- Is the power plane continuous?
- Has it many many distributed bypass capacitors to ground?
- Which kind of high speed signals is carrier on the bottom layer?
 

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FvM said:
The answer depends in part on information you are not giving.
- Is the power plane continuous?
- Has it many many distributed bypass capacitors to ground?
- Which kind of high speed signals is carrier on the bottom layer?
Click to expand...
Hi
This is a general question asked because of my curiosity.
Assume the power plane is a solid one and decaps are prvided to all the IC's present in the bottom layer.
 

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