How modify delay of a lot paths to meet constraints quickly

[nguyenvanthien]

Hi all,
I have number of path's tens that must be modified delay to meet constraints. Some paths have common points with other paths, some paths are dependece paths.
Currently, I have to trace connection of each path, find points to insert repeaters or delete repeaters. It takes a lot of time.
Do you have any idea to implement it quickly?

 

[ThisIsNotSam]

this is what the optimize commands do, they look at all paths and try to improve timing. they cannot, however, insert flops automatically. they can only improve timing of the combinational logic.

if your problem absolutely requires adding more logic stages, i.e., adding flops, then you have more labor-intensive options. you can write your own ECO-like script that looks for critical paths and inserts repeaters on them. you can go back to RTL and add flops by hand too. this is all typical engineering work.

 

[KlausST]

Hi,

the other way is to relax your constraints - if possible.

For a more detailed analysis we should see your signal path for (at least one) of the problemaitc signals .. and your according constraints.

Klaus

 

[nguyenvanthien]

this is what the optimize commands do, they look at all paths and try to improve timing. they cannot, however, insert flops automatically. they can only improve timing of the combinational logic.

if your problem absolutely requires adding more logic stages, i.e., adding flops, then you have more labor-intensive options. you can write your own ECO-like script that looks for critical paths and inserts repeaters on them. you can go back to RTL and add flops by hand too. this is all typical engineering work.

In my project, those paths are called the individual paths and constraints are individual timing. They are generated from front end team and STA team, must be met before tape out. For example, constraints are below.
- individual path 1 from ANDzz logic to RAM1 must be larger X ns
- individual path 2 from ORww logic to RAM2 must be larger Y ns
- individual path1 must be slower than path2
....

--- Updated Jan 23, 2025 ---

Hi,

the other way is to relax your constraints - if possible.

For a more detailed analysis we should see your signal path for (at least one) of the problemaitc signals .. and your according constraints.

Klaus

Regret that they are not relaxed. They are met before tape out.

 

[ThisIsNotSam]

In my project, those paths are called the individual paths and constraints are individual timing. They are generated from front end team and STA team, must be met before tape out. For example, constraints are below.
- individual path 1 from ANDzz logic to RAM1 must be larger X ns
- individual path 2 from ORww logic to RAM2 must be larger Y ns
- individual path1 must be slower than path2

I would write my own ECO script. This looks too specific to be solved in RTL.

 

[sky_siliconthink]

In my project, those paths are called the individual paths and constraints are individual timing. They are generated from front end team and STA team, must be met before tape out. For example, constraints are below.
- individual path 1 from ANDzz logic to RAM1 must be larger X ns
- individual path 2 from ORww logic to RAM2 must be larger Y ns
- individual path1 must be slower than path2
....


These timing requirements are strange to synchronous designes, timing path of the same clock domain.
If asynchrinous path (such as R/W of async sram), the RTL design may choose to assert/deassert each signal at different cycles, this will be easier to meet the timing requirements between asynchronous signals.

 

[nguyenvanthien]

In my project, those paths are called the individual paths and constraints are individual timing. They are generated from front end team and STA team, must be met before tape out. For example, constraints are below.
- individual path 1 from ANDzz logic to RAM1 must be larger X ns
- individual path 2 from ORww logic to RAM2 must be larger Y ns
- individual path1 must be slower than path2
....


These timing requirements are strange to synchronous designes, timing path of the same clock domain.
If asynchrinous path (such as R/W of async sram), the RTL design may choose to assert/deassert each signal at different cycles, this will be easier to meet the timing requirements between asynchronous signals.

Thank you for your opinion. Currently, we have to deal it at Layout phase. We can't change netlist file.

 

[ThisIsNotSam]

Then ECO is likely your best option

 

[nguyenvanthien]

Then ECO is likely your best option

Actually, I have no choice.