how many times the Nand flash could be erased?

[tictac]

Hi
I use one nand flash that made by samsung for storing data. I want to writing and reading data from the nand flash.so I need to use one address locator variable for storing the last address of last reading and writing operation.
I want to use the first block and first page of the nand flash for address locator.
By each writing and reading data from nand flash I want to update address locator. is it a good idea? and I have some questions.

1-How can I re-program a byte of one specific page of a block with out erasing that block?

2- How many times I can erase one block and program it?

By regards

 

[FvM]

Generally, NAND flash shouldn't be used for data storage without an error detection respectively correction (ECC) driver layer. Wear levelling is also recommended.

Micron e.g. specifies an endurance of 100k program/erase cycles per block when using ECC and bad block managment. In addition, with some devices the first block as guaranteed to show no errors without ECC up to 1000 program/erase cycles.

I would think about an algorithm, that embeds the address pointer information in the written data.

 

[tictac]

Hi FvM
Can you describe a little about Error detection correction (ECC) driver layer,please? how can I develop it?

I use 3 address pointer for block,page and byte for the nand flash.
By each data writing( 30 byte) to the nand flash I update the pointers.

I hold the pointers at the zero block and store the data after block 1.

can I re-program the block of the nand flash without erasing that block?

 

[FvM]

I didn't yet use NAND flash for storage, I only evaluated the technology in component identification, but opted for NOR flash in the respective project. I mainly refer to general information, that's availiable from NAND flash vendors. They give suggestion for ECC, partly providing software libraries (C-code or HDL).

1. NAND flash is programmed page wise, single bytes aren't accesible for write. As far as I understand, consecutive programming of pages is required after erasing a block. Some devices allow multiple prgramming operations of a page (only '1' to '0', of course).

2. I already answered the question, typically 100k erase cycles. But some blocks may fail before, NAND storage isn't safe without considering this fact.

 

[tictac]

In addition, with some devices the first block as guaranteed to show no errors without ECC up to 1000 program/erase cycles.

As I mentioned before,I store data each 30 byte at the nand flash.
(64 page*2112 byte)/30=4505 times of programing cycle without Erasing.

does it make a problem without ECC?

Regards

 

[FvM]

As I mentioned before,I store data each 30 byte at the nand flash.
(64 page*2112 byte)/30=4505 times of programing cycle without Erasing.

Yes you did, but as far as I understand the datasheets, it's not the way, NAND flash should be programmed, neither with or without ECC. I found a maximum of eight partial programming operations allowed with Micron chips, with other vendors it may be even less.

 

[simce]

Hello,
Partial writes should not be considered as option since if you decide to replace the chip that supports 8 writes with a model that does not support partial writes you are in deep problem. This will happen sooner or later.
As noted earlier if you have a lot of writes definitely do not use address pointer stored on only one location since it will be worn quickly (even earlier than 100k in most of the cases).
One simple mechanism can be to use index in spare area that will show which page holds the last information. Then scan all pages in the range dedicated and find the last one.
Other good solution can be to use file system for NAND that will take care for all issues that you have (wear leveling, ECC, bad block management...).
There are many choices: YAFFS2, JEFF...
BR,
Sime

 

[tictac]

Hello,
Thanks you friends.
K9F1G08U0B datasheet: <The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. >
so I should not use 4505 times of page programming operation with the same page. Is it true?

I think I should store data on the atmega128's Ram until the size of it reaches to 512 byte ,then move them to the nand flash.is it a good way?
But I Concern about losing the data because of turn off or reset of the system. one idea is that I can store data on the eeprom of the atmega128 before I move them to the nand flash.

One simple mechanism can be to use index in spare area that will show which page holds the last information.

Can you describe it a little more,please? Can I write on the spare area or it automatically do it?how can I use it?

Regards

 

[tictac]

please guide me.

 

[FvM]

so I should not use 4505 times of page programming operation with the same page

No, as said before.

The spare area suggestion, basically one of several ways to "embed the address pointer information in the written data" only solves the pointer storage problem, but doesn't help to write small data entities to a NAND flash.

I see two options:
- accept the uneffective utilization of the NAND flash, but implement an optimal handling by using a flash file system, as suggested
- use a NOR flash type, that allows individual byte writes to an erased page

 

[simce]

The indexing scheme...
Block n:
page0: DATA[Up to page size] SPARE[Index=0 ECC OTHER]
page1: DATA[Up to page size] SPARE[Index=1 ECC OTHER]
page2: DATA[Up to page size] SPARE[Index=2 ECC OTHER]
page3: DATA[Up to page size] SPARE[Index=3 ECC OTHER]
page4: DATA[Up to page size] SPARE[Index=4 ECC OTHER]
page5: DATA[Up to page size] SPARE[Index=5 ECC OTHER]
page6: DATA[Up to page size] SPARE[Index=0 ECC OTHER]

From this layout it can be seen that last data is contained in page 5 since the index has the highest value. When you are about to write 6-th data you'll populate page 6. This can continue till you write complete block or part of the block reserved for this type of data. When you fill complete block, then:
1. Make copy of this block (block n) to the next block (block n+1).
2. Erase block n.
3. Write first page of block n with page holding the highest index from block n+1
4. Write the new data in page1 of block n.
5. Then you can erase the temporary block.

If power fails between steps 2 and 3, then your software should read data from block n+1 if reads of block n are faulty (ECC error, invalid index or other read errors reported by NAND chip controller)

This way you'll have power fail safe method for updates and some kind of wear leveling.
The drawbacks of this solution is that you'll need a lot of area to store some data and if block n or n+1 fails you are out of options.

However, this is much better than nothing. My proposal for you is to use file system that has all these flaws already covered and you can write the same data a lot of times without fear that flash chip will fail or you'll loose any data.

/Simce

 

[tictac]

Hello simce
Is there any code for flash file system that can run from atmega128? can you give me a good link about it? I found some code that run under OS.but I need it that run under atmega128

I think its better that I tell that the Data is received from GPS.I store GPRMC string of received data.
Regards.

 

[simce]

I'm not sure where the code can be found for YAFFS2 (i've been using it on a project few years ago). It has version for Linux and OS Free version (i assume that you do not use OS).
The Uboot embedded loader code has a lot of FS's into the code tree which can be used to make your own port. There you can find many OS's that can be used on flash memory chips. Among them you can find YAFFS2, UBI others. I'm not sure if there is port for the MCU that you are using, but you can try.
BR.