How many clock cycles should the reset signal be asserted?

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Hi,

How can we figure out for how many clock cycles should the reset signal be active before it is pulled out/de-asserted?

Regards,
Devaraj
 

that depend of your design/ip used, and if your reset is synchrone or asynchrone?
some ip, like Cortex requires at least 3 clock cycle durations.
 

Thanks for the quick response.

I would like to know, On what basis one determines the duration of the reset (with respect to number of clocks) to be in active state so that the all the flops in the design are initialized. You have said, Cortex requires at least 3 clock cycle durations. How do they arrive that?

BTW, the reset is asynchronous.

Here is what I have some thoughts but not sure whether it is correct.
I guess the reset signal should be active for the duration equal to amount of delay in the critical path. Correct me if I am wrong.
 

When a design requires 3 clock cycles for a reset, that means, some flop without reset followed some flop with reset.
The reset signal must buffered correctly by the BE tools, and respect the timing constraints, like the critical path.
Generally, we synchronize (de-asserted) on the opposite edge of the clock (used by the flop) the reset signal to avoid the edge of the clock and the reset occur at the same time.
 
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    jaydip

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Generally designs will be with reset assertion asynchronous and deassertion synchronous
 

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