[SOLVED] How large is the dissipating ground plane on bottom layer of JESD51-7 test board

Status
Not open for further replies.

ridgemao1983

Junior Member level 1
Joined
Dec 3, 2009
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,445
From the datasheet(**broken link removed**
Thermal Resistance (θJA) eMSOP10: 45°C/W.
All numbers apply for packages soldered directly on to a 3”x3” PC board with 2 oz.copper on 4 layers in still air.

I think the test board used to obtain 45°C/W complies with JESD51-7 standard.

How large is the dissipating ground plane on top and bottom layer of this test board?
Is it "No GND on top and bottom other than DAP landing" or "Maximize ground area for top and bottom layer" ?

I can't find any related statement in the JESD51-7, if you could, can you tell me where it is in the standard ?

Thanks.
 

Attachments

  • jesd51-7.PDF
    308.7 KB · Views: 684

I don't think that the datasheet does refer particularly to the Jedec spec, except for the 3x3" dimension. TI e.g assumes 2 oz plane copper, JEDEC 1 oz. JEDEC specifies traces on top and bottom and no copper pour. It also doesn't account for thermal pads as it explicitely excludes thermal vias.
 

Status
Not open for further replies.

Similar threads

Cookies are required to use this site. You must accept them to continue using the site. Learn more…