how jerk is produced in CMOS inverter ?

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hello...

can any one tell me, how "jerk" is produced at the output of CMOS inverter during transitions and voltage level exceeds the supply voltage level ?

thanks in advance ...
 

Coupling of the input signal through the gate-drain capacitance.

Keith
 

thanks for your response ...

One more thing that i want to know that ,
whenever, we increase the frequency of input signal, the power consumption increases.
is it because of jerk that become more dominant at fast transition ? or because of more cycles that leads to more transitions ?
 

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