How is the wire routed on this evaluation board?

[lichengjun]

I am now working on designing a evaluation board for a capacitive readout chip since the board is no longer fabricated by the manufacture. The chip is used to accurately measure extremely small capacitance difference between external connected capacitors. The picture of the evaluation board is shown below.

I am not sure how the wire is connected in the highlight area.

It seems the SI pin on the chip is first connected to a via and then signal goes to the bottom of the board. From there I guess it is connected to the via under the third pin of the op amp in the highlight area. And then it is further connected to the hole SI on the left. On the first left side of the via, there is a trace which has quite large width. To the right , this trace seems isolated from and stop at the via. To the left, the wide trace is connected to the first two pin of the op amp and then connected to the holes on top and bottom of hole SI.

1. Is my description of the connection correct?
2. If I am correct, what is purpose of the wide trace? Is it for reducing the noise from parasitic capacitance?



Here I show the schematic with the same region highlighted.

 

[FvM]

It's a bootstrapped screen to minimze the capacitive load of the SI net.

 

[lichengjun]

It's a bootstrapped screen to minimze the capacitive load of the SI net.

So my description of the wire connection is correct? The wide trace does stop at the via and connected to nowhere to the right?

 

[FvM]

Yes, obviously. But the SIS screen net goes to the connector.

 

[lichengjun]

I tried to imitate the bootstrapped screen,

is there any problem with this routing? The blue line is the trace in the bottom layer.
Also I have another question about the evaluation board circuit provided by the company.
The lower right corner of the schematic below shows a simple circuit for the power supply section of the evaluation board. It seems that there are two ground, one is GND and the other is FG, there can be connected together through a jumper. The components on the board are connected to GND rather than FG.


This kind of design made me confused.
I think in this case, most area of board(copper pour) will be FG, GND only exists in several traces, am I correct?What's the benefit of doing this?

 

[lichengjun]

Yes, obviously. But the SIS screen net goes to the connector.

From the board, can you tell is the board a 2 layer board or 4 layer board? If it's a four layer board, I think the two inner layers are a VCC and a GND layer, the top and bottom layers are FG layers, is that correct?

 

[FvM]

From the board, can you tell is the board a 2 layer board or 4 layer board?

You'll know after looking at the bottom side or in case of doubt, watching the board in transmitted light. The top side photo doesn't tell.

 

[lichengjun]

You'll know after looking at the bottom side or in case of doubt, watching the board in transmitted light. The top side photo doesn't tell.

Hi, I got the picture of the bottom side of the evaluation board from the manufacture.

Now I know that the board is a 4 layer board.

I also notice that the bottom side also has a bootstrapped screen. So the signal to SI should be routed on an inner layer, either VCC or GND. I have several questions about this.
#1 Does it matter which inner layer I put the signal to SI on?
#2 If I put the signal to SI on one inner layer, should I place a bootstrapped screen on the other inner layer?
#3 For a two layer board, I was used to pour copper on top and bottom layer and make them as ground. But it seems for this four layer board, the top and bottom layer are FG, there is only one GND layer which is inside the board. Is this design reasonable?

 

[FvM]

#1 no
#2 no
You want minimal capacitance between signal and active screen, the signal line will be made as small and the screen to screen distance as large as possible.
#3 depends on the role of the frame ground in the particular design and the implemented grounding scheme

 

[lichengjun]

#1 no
#2 no
You want minimal capacitance between signal and active screen, the signal line will be made as small and the screen to screen distance as large as possible.
#3 depends on the role of the frame ground in the particular design and the implemented grounding scheme

I design my PCB with layers sequence top-GND-VCC-bottom.
At the top layer, there is a bootstrapped screen, right under the screen, I route the signal to SI on the GND layer, right under the signal to SI is a piece of copper I pour on the VCC layer, right under copper layer is the bootstrapped screen on the bottom layer.

I think the piece of copper on the VCC layer will form capacitance with both top and bottom screen, as you said, I should minimize the capacitance, does that mean I should make a copper cutout on the VCC layer right under the signal to SI? In this case, there will only be signal line between the top and bottom screen.

 

[FvM]

does that mean I should make a copper cutout on the VCC layer right under the signal to SI? In this case, there will only be signal line between the top and bottom screen.

Yes, the cutout is necessary, also a sufficient clearance (e.g. 0.5 - 1 mm) for the SI signal on the GND layer.

 

[lichengjun]

Yes, the cutout is necessary, also a sufficient clearance (e.g. 0.5 - 1 mm) for the SI signal on the GND layer.

Thanks for your reply. I have one last question, should I connect anything to the SIS connector? This chip is used to measure the difference between two capacitors.

 

[FvM]

If the application involves a sensor cable of some length, SI should be screened with the screen connected to SIS.

 

[D.A.(Tony)Stewart]

If you understand the mechanisms, then you can understand what to do.

The technical term bootstrap is also called Guarding, which is common for improving signal quality for shielding.

When the shield contains a buffered version of the signal the load current from the trace and cable dielectric current on the original signal is cancelled by making it common to both and yet the buffer provides a low impedance relative to the stray capacitance of the interfering signal.

So when the differential voltage, rate of change is null the current is null and thus is effectively the same as a cable with null capacitance. in other words Ic=C*dv/dt

Thus the active guarding also nullifies the cable capacitance.

Since this is method is intended for low frequency signals, cable length delay is usually insignificant and its impact on phase shift.

Later I decided to include a quick search for backup info. http://www.sigcon.com/Pubs/news/15_02.htm for you.

Another limitation is signal amplitude and current limit of slew rate on buffer to drive the cable capacitance for Ic=C*dv/dt and stability of the unity gain Op Amp measured as Gain margin. Normally 30 deg min or 60 deg min offers good stability, and this only becomes significant if the signal uses step pulse with broad spectrum. I would not expect this for a capacitance measurement circuit rather I would expect a constant current source signal at a fixed frequency to measure differential capacitance attached to the cable.

 

[lichengjun]

If the application involves a sensor cable of some length, SI should be screened with the screen connected to SIS.

Sorry, I am not quite clear about what you said this time.
I attached a photo. **broken link removed**

By comparing to the schematic of the board,
**broken link removed**
I am clear now that the blue wire is connected to Cx1, the brown wire is connected to Cx2 while the white wire is connected to the common of Cx1 and Cx2.

From this photo, you can see that the one SIS connector is connected to a yellow wire. I wonder what the yellow wire is connected to on the other side?

 

[FvM]

No valid attachments, unfortunately.

 

[lichengjun]

No valid attachments, unfortunately.

The PCB is shown below

The schematic is here.

 

[lichengjun]

No valid attachments, unfortunately.

I checked some material, for this guarding trace typically people connect the screen to earth.

But the author told me
"The op-amp output is the source of shielding voltage.

The yellow wire is connected to the basement of the package and
device chip substrate.

I assume that the SIS net needs to have same voltage (potential) with the SI net to reduce parasitic charge on the SI line
that is biased at Vcc/2 not at 0V."

Which one is right? Isn't the basement of the package be 0V?

Thanks in advance.

 

[FvM]

Can't be answered without knowing the sensor geometry.