Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How is the timing of this SC Sigma Delta Modulator Set

Status
Not open for further replies.

Puppet123

Full Member level 6
Full Member level 6
Joined
Apr 26, 2017
Messages
356
Helped
22
Reputation
44
Reaction score
21
Trophy points
1,298
Activity points
4,345
Hello,

Please see attached picture.

What is V in the clocking - ie. 2d/v and what is the timing of the reset clock ? When is the reset clock set, how long and why ?

Is is reset every OSR clock cycles ? Also isnt just setting an ideal capacitor with initial condition zero in simulation the same as setting a reset signal ?

Thank you.
 

Attachments

  • reset.png
    reset.png
    28.1 KB · Views: 82
Last edited:

Hello,
Could you provide the datasheet or any document explaining the component, I think it will be easy for the community to refer to the datasheet than watching your picture.
 

14-bit low-power Analog-to-Digital Converter (ADC) for sensor applications.
Frequency scalable by 1000 times from 1.67S/s to 1.67kS/s.
ADC achieves 91.8dB peak SNDR

No datasheet, it is from a thesis.

Any other information required ?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top