How is netlist simulation for ASIC design carried out?

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Netlist Simulations

Can any one explain me how is netlist simulation for ASIC targeted design is carried out.

Meaning exact details ...file extension ...tools used ...library files details etc ,....exact ...details pls

Cheers,
Gold_kiss
 

Netlist Simulations

Assume the Verilog RTL file is: design.v
after the synthesis verilog netlist: design.vg
you may simulate the netlist with the same simulator
, the same testcases, as you simulate the RTL code,
except include the library from the vendor.
 

Re: Netlist Simulations

Can you make your problem more accurate?
Normally when we say simulation,it means function or gate-level simualtions with our testvectors or test programs.
As for digital,the simulations tools are many,such as Active-HDL,Modelsim,
Debussy,NC-verilog,VCS......
 

Netlist Simulations

use the netlist module instead of the origin code, annotate the sdf or psdf, u may sumulate the netlist by running the verilog or vcs.
 

Re: Netlist Simulations

If your synthesis script is good enough I think your netlist synthesis will always pass.
just add sdf back_annotation will conform to the synthesis's timing result.so I think post_layout simulation is more important.
 

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