How is biasing done in this ckt?

[aryajur]

This is the common TIA. How is the biasing Vgs of M1 set in this circuit. Do we have to design the circuit so that Vout = Vgs of m1 according to our chosen bias point? Or do we have to bias it with another circuit and use a coupling capacitor??

 

[bimbla]

When Fin increases above the cut-in voltage of M1, it will turn on.

bimbla.

 

[aryajur]

what is "Fin"

 

[truebs]

The gate signal for one FET is fed from the second FET which is recieving the gate pulse as ground.

Its a simple multistage FET biasing,please refer any book on Basic Electronics that deals with FET biasing.

 

[aryajur]

Sorry Didn't understand what u r saying. Refer me a book, which will show the biasing of this circuit. Also once again my question is not about analysing the circuit, but how to design it. How is the biasing of M1 designed?

 

[derekqiao]

u can caculate the operation points and select device size. If the size is suitable, Vout and vgs1 can be stable.

 

[pixel]

For DC point you dont have input current, and Rf current is 0.
Output voltage same as Vgs1.

 

[dsjomo]

The gate voltage is defined through resistor Rf. Vg of M1 should be equal to Vout becuase no current flows through Rf, so the voltage drop on Rf is 0.

 

[ccw27]

So this is a self-bias ckt? All you need is a supply voltage?

 

[dsjomo]

I2 = K2(Vgs2-Vt)²
=>Vgs2=√(I2/K2)+Vt

for the same reason
Vgs1=√(I1/K1)+Vt

And Vs2 = Vg1 = Vgs1

=> Vdd = I1RD + Vgs2 + Vgs1

and I2 is the given bias current, so I1 can be solved. Use I1 to derive Vs2.

 

[lunren]

This is a negative feedback circuit includin one common source stage and one source follower. We should make sure that the DC output of the second matches the DC input of the first stage.