How is a multiplexer synthesized

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putra_sena

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I want to know the how a mux is synthesized...how to arrive at the depth of logic for, say, a 4-1 mux with sel[1:0]. in general, given N inputs and M selects and 1 o/p, how do we arrive at logic levels.

thx in advance...
 

The mux will be synthesised as a set of AND , OR and NAND gates...try synthesising the design using Xilinx to view the RTL schematic
 

This should answer all or most of your questions: **broken link removed**.
Or go directly to **broken link removed**.
Or **broken link removed**.

SOME OF THE CIRCUITS HAVE ARTICLES THAT EXPLAIN THEM.

Good luck.
 

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