How I2C will get priority for different masters?

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amitk3553

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Hello friends,
We say I2C is multi-master.So i wnt to know one thing that in I2C, how the priority will set ?Means which master is to select.Please give Details.Thanks.



Regards
Amit
 

The one who sent out the first bit data with value 1'b0.
For example: M0 and M1.
M0 send bits: 1 1 0 0 1 0 0 0
M1 send bits: 1 1 0 0 1 0 1 0
For the first 6 bits, they send the same data, arbitration is still go on.
For bit 7, M0 will get the the IIC bus as it send out "0", and M0 will go on the send the remain bits. While M1 will abort this transaction and try it later.
 
Thanks friend for your response,
Its very helpful.
Now There's another issue that if different masters like 3 in number want to communicate with 3 different slaves ,then How would priority be set ?Thanks again



Regards
Amit
 

Keep in mind: the priority is set by the rule: the master who send out the first "1'b0" will get the bus. Take the before example for example. M0 want to r/w S2 and M1 want to r/w S1.
Then, at bit7, the arbitration is done, and M0 get the IIC bus. Then the data transfer between M0 and S2 will finish.
And M1 will retry the transfer (betweeen S1) later.
 

first there is Start bit then address of slave ,then RW and after that ACKNOWLEDGEMENT(that slave is identified)
Now I want to know this procedure is followed for all masters which want to communicate or followed only with one master who gets the priority...
My Question is that in the above sequence(underlined) where the priority machanism will come?
As you are saying that Every master will send bits(which ?data bits or address bits) .....And Every master will follow this sequence to get priority machanism or only Single master after getting priority will follow this sequence.PLEASE CLARIFY THIS.

Regards
Amit
 

There's no principle difference between data and address bits, both are just bits transmitted on SDA. The arbitration mechanism hits on the first bit mismatch, when both masters are sending different addresses, this happens already in the address phase of the protocol.
 

k thanks..
 

amitk3553 said:
k thanks..
Click to expand...

Hello friends,
Again there is one issue in priority :

If we have 4 masters,One slave
And all masters have same address bits,And all have same data bits,Two have R/w - 0 and two have r/w-1,
Which out of 4 masters will communicate with slave????
Means how priority would depend on R/W?
:?:

PLEASE REPLY.
 
Last edited:

Hello friends,
Again there is one issue in priority :

If we have 4 masters,One slave
And all masters have same address bits,And all have same data bits,Two have R/w - 0 and two have r/w-1,
Which out of 4 masters will communicate with slave????
Means how priority would depend on R/W?


PLEASE REPLY.

- - - Updated - - -


Suppose There are two masters and one slave. Two masters have same address bits,same data bits ,one master M0 wants to read(R/W=1) and other M1 wants to write(R/W=0).

Then In this case Which master will get priority .PLEASE RESPOND.THANKS
 

What do you mean with "use the priority scheme over R/W bits"?. In your discussed scenario, the master that sets write operation (R/W = 0) wins the arbitration, the master intending to read stops the bus access. If there are still than 2 or master sending the same bit sequence, arbitration continues. Exceptionally multiple masters can proceed with identical data until the stop sequence.
 

FvM said:
Same scheme as before. 0 is dominant, 1 is rezessive.
Click to expand...


1)One more thing is...that in case of arbitration,after master is selected ,Again there will be transfer of slave address?....or slave would be selected during sending address,R/w bit further to slaves during arbitraion.

2)When slave address is going towards Slave, then clock will SCL clock(Generated during arbitration) or master clock which is selected in Arbitration...??
 

Arbitration isn't a separate step in in I2C operation. It simply occurs during regular master operation, provided the master is prepared to delay SCL.

SCL is always generated by wired AND of all connected masters and slaves. In so far there's no "master clock" in contrast to SCL. Physically, the master clock is a timer that sets the low and high pulse widths send to the bus.
 
At one time only one master will be active. there is no priority concept.. completely software configurations. the master who sends out the start bit first will get the BUS and bus will be blocked and all others acting as slave now...
 
At one time only one master will be active. there is no priority concept.. completely software configurations. the master who sends out the start bit first will get the BUS and bus will be blocked and all others acting as slave now...
Click to expand...
You'll notice that priority in bus arbitration is verbosely discussed in the I2C specification.

But this part of the specification becomes only operative in special cases, when two or more masters are starting the bus access simultaneously. If this is likely to happen at all depends on the application enviroment. But you'll be surely able to design a system where it happens occasionally or even frequently.
 

dean_winchester said:
At one time only one master will be active. there is no priority concept.. completely software configurations. the master who sends out the start bit first will get the BUS and bus will be blocked and all others acting as slave now...
Click to expand...

Means you are saying there will be 1 to 0 for one master and all ones for all other masters ,then 1's from maximum masters and 0 from one master on positive level of SCL come ,Then I think there will be collision.
 
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