If you have a 2X input clock, I've done a quadrature static
divider using half-latches that worked pretty well (>1GHz in,
>500MHz out, 0.5um SOI @ 3.3V) as the clock recovery
phase-field generator for a burst-mode SERDES. The half-
latches (and all FFs) are bare-clocked with a 2-phase
(CK, CKb) clock input, the split pair is generated at the
ECL-compatible input buffer. So flipping clock phase is
just a pin swap. Each half-latch Q output is one of the
quadrature phases. The thing operates as a ring counter
with an inverter wrap.
No, I can't show you deep detail. We jus' po' sharecroppers.
I am sure that you could get a CML/SCL scheme to run above
2GHz. Bang-bang CMOS, that could be tricky.