How i connect 2 Spartan 3XCS3S400 boards?

[nikd]

Hello,
for some months i have started to experiment with VHDL, and tried and made examples from the book "Learning By Example Using VHDL - Advanced Digital Design" by Richard E. Haskell and Darrin M. Hanna.

I managed to make the UART example in this book work with my PC RS232 and my terminal program, sending and receiving.
However when i try to connect 2 Spartan 3 XCS3S400 boards together with a male-male RS232 cable it doesn't seem to work.
Managed to get a package counter in this design, but when i load the Programming (.bit) file in both FPGA's then what happens is that both FPGA's count in the same time the package data, but can't control the flow.

Any source or advice?

Thank you

P.S.
VHDL Code is available to send.

 

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Why don't you add the code to your post between syntax tags?

[syntax=vhdl]...your code...[/syntax]

Did you try running the designs together in a testbench, that is usually what people (at least working engineers) do.

Does your male-male cable correctly cross connect the TX/RX lines and not run them straight through.

 

[nikd]

Thank you very much i have connected them straight, so it needs to be crossover. The Rs232 cable i have is DB9M/DB9M 1.8Μ. About the code it is 8 vhdl files will try ti give a link click here.
The code has been modified from the original LBEBooks in the part of input from keyboard or the board switches.

Thank you very much again.

 

[nikd]

Have tested crossover RS232 cabel, with Rx -> Tx and Tx -> Rx. Effect still same. So guess the problem is in VHDL code which don;t send direct to other UART the data it has in buffer.

Thank you

 

[BradtheRad]

Did you try the simplest configuration? I used a null modem years ago to send program listings from my VIC-20 to my Macintosh. It does without the handshaking protocols.

Only 3 wires go between your devices (ground, send, receive)(Send & receive are crossed over). Install jumpers at each end in such a way to make the devices think that proper handshaking was done. Pinouts for a DB9 null modem can be found on the internet.

Make sure your devices have compatible settings: data bits, baud rate, full/half duplex, parity, etc. Start with a slower baud rate rather than the fastest.

 

[ads-ee]

Just downloaded the code and took a look at it.

You've got a number of issues.

• You are using a clock divider instead of using a DCM/PLL/MMCM. Without the proper constraints it may have setup/hold time issues as the tools won't generate a clock from the output of the FFs used to create the divider and therefore may not correctly account for the skew of the two output clocks. Generating clocks in this fashion is not recommended in FPGAs.
  
• You don't have a testbench.
  
• You have a debouncer but then never use it to debounce your button signals. Typical buttons do not switch cleanly and many not settle for upwards of 10ms. Your q counter in the clkdiv divides downs (100 MHz?) the input clock to a 50 MHz and not a 190 Hz clock but instead a 100e6/(2**17) = 762.9 Hz clock, which with the 3 register delay only gives you 4 ms of settling time, but then you never use it anyways.
  
• Your bit_time looks wrong, but I might just be misunderstanding your code at first glance. It looks like you are not attempting to receive as the comments suggest at 9600 as the baud rate ends up being 50e6/2600 = 19230.

You really need to write a testbench and connect your design in loopback to check that it works correctly.

 

[nikd]

Yes i use a 3-wire cable made one crossover with Rx to Tx and vice versa. However problem remains. Thank you.

 

[nikd]

Thank you, to be honest i am mixed up, i see that when i connect my FPGA via RS232 to my PC and run the terminal program the code seems to work correct as i expect, i send and receive data as it should do.

About testbench i am afraid that i am inexperienced and i don;t know how i run it and see results.

 

[nikd]

Thank you for answer what mixes me up is that when i connect my fpga to PC it seems that the code works as it should be receiving and transmitting at 9600-8-N-1.

 

[nikd]

Solution found ! After hours

U4 : test_tx_ctrl
	port map(
		clk => clk50,
		clr => clr,
		go => btnd(0), --rdrf_clr,
		tdre => tdre,
		ready => ready
	);

Managed to achieve 2 fpga communication.

Thank you all for your valuable consult !