Jun 9, 2015 #1 N nehajoshi Newbie level 3 Joined Nov 16, 2010 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,301 How frequency, cell area, leakage power impacts physical design goals in VLSI flow?
Jun 9, 2015 #2 J jbeniston Advanced Member level 1 Joined May 5, 2005 Messages 460 Helped 106 Reputation 214 Reaction score 73 Trophy points 1,308 Activity points 3,494 They are the goals, usually.
Jun 11, 2015 #3 N nehajoshi Newbie level 3 Joined Nov 16, 2010 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,301 jbeniston said: They are the goals, usually. Click to expand... Thank you for your response. So do they impact each other? If so, how? Kindly let me know.
jbeniston said: They are the goals, usually. Click to expand... Thank you for your response. So do they impact each other? If so, how? Kindly let me know.
Jun 11, 2015 #4 A artmalik Full Member level 5 Joined Mar 13, 2013 Messages 253 Helped 91 Reputation 182 Reaction score 85 Trophy points 1,308 Location San Diego Activity points 2,997 if you want to increase the frequency of the design....you have less time period to complete the task...so you need faster gates which will increase the area ....bigger devices mean higher leakage current.
if you want to increase the frequency of the design....you have less time period to complete the task...so you need faster gates which will increase the area ....bigger devices mean higher leakage current.