How does variables and signals get synthesized ?(VHDl)

Status
Not open for further replies.
V

vikas_lakhanpal27

Member level 1
Joined
Jan 16, 2008
Messages
39
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
1,522
Variables in VHDl

Hi All,
Few days back in one of the book I red that Variable does not take any harware after synthsis. As per me Varaible takes hardware. What does you guy think?

Thanks and Best Regards,
Vikas
 

Variables in VHDl

Variables are like temporary references to signals. examples can be check at
group:comp.lang.vhdl Bromley on variable in state machine
they can be synthesized.
 

Re: Variables in VHDl

The way in which a variable or signal get synthesised depends upon the code entirely... its does not depend upon whether we use a signal or a variable...
 
Re: Variables in VHDl

Hi.

How variables and signals gets synthesized depends upon your code.
But only signals are used to connect between different modules.

Regards
freak
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…