How does variables and signals get synthesized ?(VHDl)

[vikas_lakhanpal27]

Variables in VHDl

Hi All,
Few days back in one of the book I red that Variable does not take any harware after synthsis. As per me Varaible takes hardware. What does you guy think?

Thanks and Best Regards,
Vikas

 

[linkfox]

Variables in VHDl

Variables are like temporary references to signals. examples can be check at
group:comp.lang.vhdl Bromley on variable in state machine
they can be synthesized.

 

[lordsathish]

Re: Variables in VHDl

The way in which a variable or signal get synthesised depends upon the code entirely... its does not depend upon whether we use a signal or a variable...

 

[vlsi_freak]

Re: Variables in VHDl

Hi.

How variables and signals gets synthesized depends upon your code.
But only signals are used to connect between different modules.

Regards
freak