how does the layout change connecting Bulk to ground or source terminal

[circuitking]

Hi, I wanted to figure out what happens connecting bulk to source or ground terminal in the below circuit. In DRC, it doesn't give any error for the same layout, whether I connect the bulk to source or ground in schematic.

Are there any rules when to connect bulk to source or ground? I usually connect NMOS to ground in all my design, but I want to correct myself if I am doing wrong.
I know connecting bulk to source (if source is higher potential than ground), the threshold voltage decreases. But doing so, do I have to have another P+ contact in the layout for that particular NMOS? In that case, with respect to layout area, it is advantageous to connect all NMOS bulk to ground itself, so that not many P+ contacts are needed.

 

[dick_freebird]

You can save area when rules allow butted N+/P+ regions within a single active area. Else it's going to see active-active spacing S to B minimum. PCells I've seen have tap geom options. When VT match is critical you would want any B-S butting to be identical as there can be autodoping locally.

 

[FvM]

Does your CMOS process provide isolated NMOS substrates? You need a triple-well process with p-well in n-well to achieve this.