giggs11
Member level 3
Hi,
EternalMan mentioned that Clock Tree Insertion is done after the STA tool reads and analyses the post-layout netlist....and this would be called Clock Synthesis?
Okay, so what you're saying is that STA would identify and instruct the layout tool to place buffers at clock branches to clock inputs...?
Thanks.
EternalMan mentioned that Clock Tree Insertion is done after the STA tool reads and analyses the post-layout netlist....and this would be called Clock Synthesis?
Okay, so what you're saying is that STA would identify and instruct the layout tool to place buffers at clock branches to clock inputs...?
Thanks.