How does "include" work in Verilog?

[Xenon02]

I've got a problem understanding how include works. My teacher told me that include isn't meant to include modules but constant values.
He said that using the same include module in many modules will make errors because the module with the same name is on 3 other modules (3 different files .SV).
I don't get it. I used includes on testbench, but I should do it. Why?
I don't understand the statement that the same name of the included module is in 3 files.
Update :
Usually I use include in testbench to add other modules for example include "Not_module.sv". But I was told to not do it. I don't know why.
Also the argument to not use include for modules. For example let's say I have a module "not_module.sv" and two other modules "ALU1.sv" and "ALU2.sv"
I need "not_module.sv" in both ALU modules. So I added include in ALU 1 and ALU 2. My teacher said that the synthesis or simulation will not know which include module to compile or something. I don't understand it. Let's say ALU1 uses the not_module to substract something and ALU2 uses not_module to add something. So why compiling ALU1 and ALU2 will complicate it when there is include "not_module.sv"?

I mean I don't quite understand the last part. Librarys ? But what is the problem with one module in two different libraries ? Because SystemVerilog only creates somekind of logic gate equivelant. In real life we use the same module like not_module in many other modules so I am confused with the fact that there can't be 1 same module in 2 different modules and it can't compile correctly. It's like it's making not_example module in alu 1, but doesn't make not_module in Alu 2 just because they have the same not_module. I don't get it

 

[FvM]

Verilog reference manual says:

The file inclusion (`include) compiler directive is used to insert the entire contents of a source file in another file during compilation. The result is as though the contents of the included source file appear in place of the `include compiler directive.

--- Updated Nov 19, 2022 ---

Including a module definition more than once generates an ambiguity.

 

[Xenon02]

Verilog reference manual says:

--- Updated Nov 19, 2022 ---

Including a module definition more than once generates an ambiguity.

I don't get it could you please give me an example ?
Because let's say I have not_module that changed input A into negative A.
So this module is used in ALU 1 and ALU 2. Now I use include in ALU 1 and include in ALU 2.
The not module takes the input and spits the output in ALU 1 in 3rd input of the multiplexer. In ALU 2 the not module takes input and spits output in the 2nd input of the multiplexer.
Now both of them are compiled. So what is the problem for the separate ALU to be compiled ? And if those alu were in one testbench for example ALU 1 and ALU 2 are in the Testbench 1. So compiling it what could cause a problem and why ? Because of the name ? The constant values can be compiled in many modules but modules can't be included in other modules. I don't get it.

 

[FvM]

The question is about different name spaces used in Verilog

You don't need to (and must not) use `include to define a module. Module names in one compilation unit become known in all compilation units of your project when you compile the unit. They reside in the global definitions name space. Constant names are in the compilation unit name space and therefore not known to other compilation units.

 

[Xenon02]

The question is about different name spaces used in Verilog

You don't need to (and must not) use `include to define a module. Module names in one compilation unit become known in all compilation units of your project when you compile the unit. They reside in the global definitions name space. Constant names are in the compilation unit name space and therefore not known to other compilation units.

I still don't get it.
It's like compiling a whole unit ALU 1 with what's inside same goes with ALU 2. So I don't get it. Like the not_module is differently connected in ALU 2 than in ALU 1. So there shouldn't be any problem using include not_model in ALU 1 and ALU2.

Can you show me somehow why it doesn't work ? Because I still don't get it. Sorry for any problem

 

[FvM]

I see two ways
1. believe your teacher and me that `include isn't mean't to insert modules in your Verilog code.
2. understand the Verilog name space concept and why it's an error to use the same module name more than once in a project

 

[Xenon02]

I see two ways
1. believe your teacher and me that `include isn't mean't to insert modules in your Verilog code.
2. understand the Verilog name space concept and why it's an error to use the same module name more than once in a project

There isn't any picture like ilustration why I can't do it ?
I tried to find this answear in many forums but I still don't get it. I would like to believie it, but somehow i must add something from one module to another module. So I thought include would work pretty good like in C++ or other programming language.

I didn't think about it that much but when my teacher told me to not do it then I didn't understand why. Like one module in 2 different modules do 2 different things but doesn't work.

 

[TrickyDicky]

include basically does a copy+paste of one file into another.
Try it yourself. Instead of using `include, try copy/pasting the other file into the one you're working on and see if it still compiles or makes sense.

 

[pbernardi]

He said that using the same include module in many modules will make errors because the module with the same name is on 3 other modules (3 different files .SV).

He is correct here. You cannot do this because when you include a file twice, the tool will read the file twice and will detect duplicate registers/wires/parameters/(other definition I might have forgotten).

Note, however, that there are ways to workaround this. You can, for example do the following a define file containing some defines/parameters/whatever:

parameter example1 = 8'b00001111;
`define example2 8'b11110000

and do the following:

`ifndef defines_vh
`define defines_vh

parameter example1 = 8'b00001111;
`define example2 8'b11110000

`endif

This way the tool should recognize only the first include and ignore the others.

While I haven´t ever tested this to include modules (I use only for constants in general), I think it should work (test by your own risk).