How does flyback minimum drain voltage detection occur?

[eem2am]

Hello,

I am investigating the NCP1338 Quasi Resonant flyback PWM control chip for an offline flyback power supply (Vin = 240Vrms)

NCP1338 Datasheet
****************
https://www.onsemi.com/pub_link/Collateral/NCP1338-D.PDF

here is a schematic of a flyback stage.

This chip (NCP1338) claims to be able to switch the FET on at the minimum drain voltage point, during the Vds oscillation that occurs after the flyback secondary has finished conducting.

This chip claims to be able to do this by its gate drive pin sensing the current from the intrinsic Cds capacitance.

The datasheet says it can detect when the Cds current reverses, (corresponding to the minima of the Vds oscillation) –and will then switch on the FET,

However, I have done a simulation of a discontinuous mode flyback (with a different PWM controller) and I have added a Cds capacitor.
-the current in this capacitor does NOT reverse at the point of minimum Vds.

-so how can the NCP1338 possibly work as it says it should?

Here is the simulation file in LTSpice
***************
https://www.2shared.com/file/8588702/564ff474/FLYBACK_MAINS_LED_CLAMP_141009.html

Here is the Cds current , which doesn’t reverse at the Vds minima.
********************

 

[FvM]

Here is the Cds current , which doesn’t reverse at the Vds minima.

Of course it reverses. Alhtough hard to detect in the shown waveform scale. Vgs is constant in the respective interval, so Icds = Cds*dVds/dt, it changes polarity at Vds = min.