How does double data rate work?

[katastic_voyage]

I understand it transmits on the positive AND negative clock pulses. But how do you design the associated logic gates and so on to take advantage of that pulse?

The difference in routing I'm having trouble wrapping my head around.

Say we have a DDR memory module.

Does everything inside react to both pos/neg clock pulses and the rest is routed the same? Or is there a special clock input that then produces an internal clock pulse for both of the external clock pulses?

And finally, let's take it further. How does a circuit "function" in a QDR (quad-data rate) setup? I know it uses 90 degree increments of said clock but then what? How are gates routed to take advantage of it?

Oh, one final question: If double-data rate allows transmission at the same rate as the clock frequency, how does QDR transmit twice that? If you can transmit twice the clock speed, why not just double the clock speed?

 

[FvM]

What are you designing? Memory module, host adaptor?

Generally speaking DDR or QDR only specifies the relation between a clock signal and data lines. It doesn't say how the logic is implemented. Both host memory interfaces and memory modules are mostly using a multiplied PLL clock internally. Clock phases are trained for maximal sampling margin automatically, in DDR3 even individually per bit.

 

[katastic_voyage]

That is impressive!

I'm not designing. I'm an ME trying to learn EE/CE in my spare time. I'm just trying to find some insight into how those circuits are implemented as I can only find very abstract/conceptual descriptions of them.