How does audio ADC PCM1808 in slave mode know what rate to sample the input at?

[matrixofdynamism]

The datasheet of PCM1808 contains table 1 found **broken link removed** on page 11. It lists the possible sampling rates as 8, 16, 32, 44.1, 48, 64, 88.2, 96 KHz. It then lists the master clock values required for these different sampling rates. If we look at it e.g 16.384MHz master clock can give 32KHz sampling frequency (512 fs) or 64KHz sampling frequency (256 fs). It then says that "The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS in slave mode" but it is not clear how.

I have the following questions:

Precisely what determines the sampling rate of the PCM1808 in slave mode? Why are there only such discrete values as 8, 16, 32, 44.1, 48, 64, 88.2, 96 KHz?

If I connect a 16.384MHz crystal as master clock source for the PIC microcontroller as the master and PCM1808 as the slave, how will the PCM1808 know what rate to sample the input signal i.e 32KHz or 64KHz as both have 16.384MHz value in their respective row?

When does the PCM1808 actually sample an input signal, is it when the LRCK is asserted low or is sampling the input signal contiously? i.e if I read the ADC at time T, which sample in time of the input signal am I reading?

At what rate can one read the data from the ADC? e.g if sampling rate is 44KHz, does the PIC microcontroller being the master device need to leave everything else and just read the ADC at this rate? Can the ADC use timer interrupts for this purpose?

 

[FvM]

1. The discrete Fs numbers are industry standard audio sampling rates. The converter can work at different rates, the essential point is the master clock to fs ratio.

2. The internal fs divider is switched according to the actual BCLK rate.

3. A sigma-delta converter is continuously sampling the input signal and generating the output data stream by a decimating filter. According to the filter characteristic, the aquisition window has a width of about 35 samples.

 

[matrixofdynamism]

Thankyou teacher FvM, this has clear a lot of questions. About (3), I think you wanted to say 64 samples as the datasheet says "Oversampling Decimation Filter, Oversampling Frequency: x64". If we have a 16.384MHz master clock and the ADC is carrying out Oversampling Frequency at x64, this means the ADC has sampling rate of 256KHz?

Since the master device is fed the same 16.384MHz clock in this example, at what rate is the BCLK clocked out of the master device if we want the sampling rate of the ADC to be 32KHz?

By the way, I see that these audio ADCs and DACs are always boasting about not generating pop noise when the device performs certain functions or perhaps power up/down. Why should this pop occur in the first place? is it that when the sound is suddenly turned off, it will generate a lot of frequency components which one will hear as an inconvininet pop?