How does a digital phase lock loop function?

[scdoro]

hi everyone,

Qn(a): How does a digital phase lock loop function?

Qn(b): Can a digital phase lock loop be used be used to synchronize asynchronous data with the clock? If yes, how?

thanks

 

[Davood Amerion]

Phase lock loop

this is a sample IC which use DPLL :
**broken link removed**
and this one used to syncronized PCM data at reciver side.
I hope this is helpful.

 

[scdoro]

Re: Phase lock loop

i am actually trying to tap the keyboard clock from the PS/2 KBD pin. and use it to synchronize with asynchronous data running at baud rate of 9600bits/sec.For each data frame transmitting, at each trailing edge of the clock,it will fall/sampled on the middle of each data bit..It will then be sent to the keyboard port.

P.S: the IC chip for the website you gave me seems to be obsolete.Are there any other schematics or IC chip that will suit my needs..

thanks a lot.

regards

 

[Davood Amerion]

Phase lock loop

That link was for finding DPLL principle.
I dont underestand you problem very well, but as i know asyncronus serial port dont need DPLL!