How do you simulate the start up circuit for a bandgap?

[ccw27]

ptat self biased cascode -patent

How do you simulate the start up circuit for a bandgap? Do you run a transient simulation and ramp the Vdd from 0 to Vdd? How do you check whether the start up circuit has failed or not? What other simulation tests should you do in terms of process, temperature and voltage variation?

Thanks

 

[leebluer]

Re: Bandgap Design

I simulate the startup of Bandgap with a PWL source. Like your say, the source should ramp the Vdd from 0 to Vdd. And I simulate the circuit under all the process corners with different PVT to find whether the startup circuit works properly.

I think you could throw off the startup circuit to validate the work of startup circuit. But firstly your should know why you need a startup circuit in your design.

 

[hspice2008]

Re: Bandgap Design

I use pwl source ,let vdd rise from 0v to 3v in several ns . then I can see whether the bandgap output can reach its final value without ripple, if have ripple, I will change or compensate the circuits, to eliminate it

in addition , I will run all conners to test the startup of it

 

[ccw27]

Re: Bandgap Design

How do you typically size the transistors for this startup circuit for example?

Thanks

 

[Fom]

Re: Bandgap Design

Where is charging device for A or B node?

 

[ccw27]

Re: Bandgap Design

Where is charging device for A or B node?

self-bias circuit, PTAT current mirror, op-amp

 

[jiangwp]

Re: Bandgap Design

If the A or B is used as bias for gate of PTAT current, i think the circuit will not work.

Generally , the statup circuit generates the current for core circuit, once the core circuit work normally , the startup circuit is isolated from the core circuit.

AS you draw , the A or B will effect the core circuit when the core circuit work normally.

Please draw whole circuit.

 

[ccw27]

Re: Bandgap Design

The A or B is not used to bias, but used to start the self biased cascode. The self bias circuit will then bias other parts of the circuit. Probably didnt express well last time.

 

[ccw27]

Re: Bandgap Design

Here is a paper that used this start up. Can anyone help me on how I can go about sizing the transistors in the startup circuit?

Thanks

 

[gevy]

Re: Bandgap Design

I use PWL sourse and voltage rise from 0 to VDD for various rise time: several ns, several us and several ms. It simulates various conditions of start-up.
It is important !

 

[triquent]

Re: Bandgap Design

When I let vdd rise from 0V to 2.5V, I got a ripple or spike output about 530mV(stable Vref=1.26V, the spike is 1.79V ). Seems the ripple is too big. How can I reduce the ripple or spike? How to change or compensate the circuit?

I use pwl source ,let vdd rise from 0v to 3v in several ns . then I can see whether the bandgap output can reach its final value without ripple, if have ripple, I will change or compensate the circuits, to eliminate it

in addition , I will run all conners to test the startup of it

Added after 13 minutes:

when we simulate the bandgap voltage reference, usually we put a capacitance at the output(Vref). Does this capacitance represent the parasitic capacitance? So it is put there just for simulation purpose and for real case? Or it will be implemented by layout?

 

[Teddy]

Re: Bandgap Design

current to the PMOS should be > cca 0.5uA
decent scaling could be: Pmos 10/10 ;
Left NMOS : 50/10, right NMOS 10/10, MS 3/1

enjoy!

 

[IC_Lee]

Re: Bandgap Design

current to the PMOS should be > cca 0.5uA
decent scaling could be: Pmos 10/10 ;
Left NMOS : 50/10, right NMOS 10/10, MS 3/1

enjoy!

why should the current be larger than 0.5uA?
thanks

 

[cetc1525]

Bandgap Design

I think the simulate of startup is not nessary.for you can judge it by hand.I think the stable of the circuit is important.

 

[ccw27]

Re: Bandgap Design

I have a question. Does it matter what Vbg is? i.e. does it matter if you have 1.2 or 0.6 V Bandgap voltage reference? You normally reference current to other parts of the circuit not voltage. Or is bandgap voltage needed somewhere?

Thanks

 

[jordan76]

Re: Bandgap Design

Hi ccw27,

Given certain circuit structure,usually Vbg is determined by fine-tuning device sizes to achieve zero temperature coefficient at typical conditions and small variation range. Whether the absolute value of Vbg matters depends strongly on your applicaitons/requirements.

Hope it helps.

regards,
jordan76

 

[ikru26]

Re: Bandgap Design

for simulating the start up circuit what u did..what are the constraints u keep in mind while simulation?

 

[cliffj]

Re: Bandgap Design

A ramp voltage from 0 to vdd,tehn you can easily check if the start up works or not

 

[andy2000a]

Bandgap Design

how to design low current bandgap ?? Vcc=3.3v
target is bandgap block =1ua
vbg= 1.25v .. if use low current design
use "CMOS circuit design layout & sim " CMOS cascode bandgap architecture

 

[crazyamd]

Re: Bandgap Design

I have a question. Does it matter what Vbg is? i.e. does it matter if you have 1.2 or 0.6 V Bandgap voltage reference? You normally reference current to other parts of the circuit not voltage. Or is bandgap voltage needed somewhere?

Thanks

BGR means the generated voltage is insensitive to temperature. in order to meet this goal, you need to size transistors/resistor to cancel out the temperature effect. so normally the output voltage won't be exactly the silicon bandgap voltage (or integer multiple).