How do you instantiate/attach the lef files into your physical design

[Gagandeep20320]

I have a doubt. How do you instantiate/attach the lef files into your physical design .


Details of my question:-
1. I used innovus to get the GDSII for the processing system.
2. I want to add an ADC (full custom) to the design. I have made the layout in virtuoso.
3. How can I pick the layout from virtuoso and place it inside my digital physical design.
Current understanding: Currently I look forward to generating a LEF file from the virtuoso and add it to the GDS placement.

But I don't knwo how to do that.

PLEASE GUIDE ME..

 

[ThisIsNotSam]

you need a tool called abstract generator. it is part of the virtuoso suite

 

[Gagandeep20320]

you need a tool called abstract generator. it is part of the virtuoso suite

Then, would I need to instantiate the LEF macro in the netlist?

I mean how would the logical connections etween my standard cell design and the Macro would be defined once I I generate a LEF file?

Could you please also tell how I can connect my MACRO to the standard cells?


Example:
1. I have 8 bit SAR ADC layout. I make the layout and get the LEF for it.
2. 8 bit output of thr ADC has to be connected to GPIO port that is implemented in RTL and hence synthesized.
3. How do I make the logical connection of these 8 bits to GPIO port bus logically/ physically.


Looking forward to hearing from you...

 

[ThisIsNotSam]

you make the connections by hand in the netlist.

once you generate the LEF, open it in a text editor and you will understand that your macro has a name and pins. just instantiate in verilog and the physical synthesis tool will understand what you are trying to do.