How do we test for a stuck_at 0 fault on the active low reset of a flop

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anjana_das

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Hello ,
How do we test for a stuck_at 0 fault on the activ low reset pin of a flop. Toggling the reset pin during capture will detect the stuck_at 1 . But what about stuck_at 0 ?

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AD
 

Hello,

We are not toggling the Reset pin in Test mode. Reset pin should be constrained and controlled through out test mode. We use only Data pin and clock pin to get the output 0 and 1.
 

It is recommended to have the reset of all flops controllable by a direct pad in scan mode, by this way the ATPG could used it to reset all flops and then the stuck_0 of rst pin of the flop is covered. The stuck_1 is cover if it could shift.

In our design the flop reset pin is connected to a pad, and few patterns (4-5) toggle the RESET pad, of course there are no clock pulse on SCAN clock during the capture cycle.

In Tessent Mentor tool, the scan reset and scan clock are noted as clock pins, which means the tool could toggle both to capture.
 
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