Reply to thread

To my understanding, this's not the task of verilog。The driven-strength of a cell, capacitance of a node will be defined in cell library(in the format of *.lib files) and be calculated by STA tools, e.g. Design Compiler, PrimeTime, Vivado.

When coding RTL, you just need to estimate the delay of your code. That's what's the HW architecture of your code, which cells will be used after synthesis, what's the connection relationship and logic delay level?

For relationship between RTL and HW, you can refer to this podcast on Youtube:

Verilog for Design and Verification:

[MEDIA=youtube]dB-A1Zqsr60, list: PLtu65peUvdoO17ar0aoSTaoCnBUHu9BK1[/MEDIA]

And for delay calcualtion, you can refer to free preview part of this course on Udemy:

STA && DC Synthesis:

[URL unfurl="true"]https://www.udemy.com/course/digital-icfpga-design-p4-sta-dc-synthesis/?referralCode=F99007C1E5B740E11E03[/URL]