How Do I Use Verilog to Calculate the Electrical Effort of a Logic Gate?

[kvnsmnsn]

I've turned my attention to timing my project. Last December I finished taking VLSI Design at Utah Valley University. On page 155 of the textbook, CMOS VLSI Design: A Circuits and Systems Perspective, by Neil Weste and David Harris, it says a rough estimate of the delay of a gate can be expressed as (d = f + p) and (f = gh) where (p) is the parasitic delay, (g) is the logical effort, and (h) is the electrical effort. Page 156 says that (g) for a two-input NAND gate is 4/3, and (p) is 2. (h) is defined as the output capacitance divided by the input capacitance. The charts on page 156 and 157 give me enough information to calculate the parasitic delay (p) and the logical effort (g), and I can use those values in Verilog to calculate most of what I need for a delay for a gate (like a two-input NAND or a two-input NOR), but how do I calculate (h)? How can I look at my Verilog code and figure out what the output capacitance and the input capacitance is so that I can divide the former by the latter?

 

[sky_siliconthink]

To my understanding, this's not the task of verilog。The driven-strength of a cell, capacitance of a node will be defined in cell library(in the format of *.lib files) and be calculated by STA tools, e.g. Design Compiler, PrimeTime, Vivado.
When coding RTL, you just need to estimate the delay of your code. That's what's the HW architecture of your code, which cells will be used after synthesis, what's the connection relationship and logic delay level?
For relationship between RTL and HW, you can refer to this podcast on Youtube:
Verilog for Design and Verification:

And for delay calcualtion, you can refer to free preview part of this course on Udemy:
STA && DC Synthesis:

https://www.udemy.com/course/digital-icfpga-design-p4-sta-dc-synthesis/?referralCode=F99007C1E5B740E11E03

 

[D.A.(Tony)Stewart]

Logical Effort

Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed t

www.elsevier.com