How do I tell Design Compiler a signal is a constant?

My Verilog design has a master control signal that changes the operation of the chip. Since this signal does not toggle while the chip is running, I want Synopsys Design Compiler to treat it as if it were constant, and not perform any timing optimizations or needless buffer insertion for it.

What is the command I need to use for this? Is it some sort of set_false_path or set_max_delay? I'm a little scared of the set_false_path syntax since I've heard that doing it wrong could end up removing the timing constraints on every gate that my control signal touches, and I do not want to do that.

set_case_analysis

Yes, In DC we can mention a signal/port is constant by set_case_analysis.

Please refer DC user guide to know more on its usage.

regards,
freak

Other option, you can instruct tool to not to optimize the network associated with fanout of the constant signal. set_dont_touch_network on the constant signal. The tool doesnt insert the buffers as well it wont optimize away .

Correct me if i am wrong.

Regards,
Sam

I think doing either set_case_analysis or set_dont_touch_network have some possible issues

1. If with set_case_analysis, there may be some unwanted optimization in the fanout of the "master control signal". If it's really static, why not change it to a constant

2. If with set_dont_touch_network, the logic in the fanout may not get mapped to gates (remain as GTECH cells)

I suggest the following options
1. No extra constraints. Just let DC treat it as single cycle timing from the "master control signal"
2. If it fails timing, I suggest add a set_multicycle_path. Just remember to also set properly for hold timing (e.g. if mcp_setup = 3, use mcp_hold = 2), and ensure the "master control signal" is really stable before the rest of the chip operates.
3. If this signal is heavily loaded, you can add a set_ideal_network (you can also use -no_propagate option), and then let the backend guys insert the buffer tree

Hope these help

It's definetly enough not to constrain that input in any way. The synthesis tool will not optimize in terms of timing the paths that are starting from that input (only area, power, if you have constraints for them). The time allowed for these paths will not be a "single cycle" but an infinite amount of time so there is no way to get here a negative timing slack.
set_case_analysis will not help you in any way.

Do you have any indications, that setting a constant value to a signals isn't sufficient to achieve what you want. Synthesis tools I'm working with are intelligent enough to be aware of the constant nature of a signal.