How do I synthesis RTL to a desired ICG cell

[wy21century]

I wrote a verilog module in RTL and use it to abstract high level clock gating function. I want to replace it to a ICG cell in synthesis in order to ease DFT and PR flow. But when I tried with Magma, the tool complain 'no delay node found, won't do any clockgating'. Anything do I miss or any mistake exists in below code?


module ClkGate (

CLK,
RESETn,
ClkEnable,
scanmode,
GatedClk

);

input CLK;
input RESETn;
//synopsys async_set_reset RESETn
input ClkEnable;
input scanmode;

output GatedClk;

wire ClkEn;
reg ClkEnT2;

assign ClkEn = ClkEnable | scanmode;

always @(CLK or RESETn or ClkEn) begin
if (RESETn == 1'b0) begin
ClkEnT2 = 1'b1;
end
else if (CLK == 1'b0) begin
ClkEnT2 = ClkEn;
end
end

assign GatedClk = CLK & ClkEnT2;

endmodule

 

[subhash_chevella]

Hi,

You can hard-instantiate the ICG cell in the desing.
before synthesise, modify the RTL code as shown.

'define useICGcell

module ClkGate( <declare the inputs & iouputs>);
if(useICGcell) <instantiate the ICG cell>
else <the code written for clock gating module>
endmodule

As you instantiate other module in design, in the same wat instantiate ICG cell. You will get ICG cell information from the .lib file.
You can choose ICG cell as well.
It will work. I tried in this manner. It worked for me.

regards,
Subhash

 

[wy21century]

Hi,

You can hard-instantiate the ICG cell in the desing.
before synthesise, modify the RTL code as shown.

'define useICGcell

module ClkGate( <declare the inputs & iouputs>);
if(useICGcell) <instantiate the ICG cell>
else <the code written for clock gating module>
endmodule

As you instantiate other module in design, in the same wat instantiate ICG cell. You will get ICG cell information from the .lib file.
You can choose ICG cell as well.
It will work. I tried in this manner. It worked for me.

regards,
Subhash

I would not prefer this method since I want this file is free to any process so that it can be reused for other projects w/o any modification.

 

[subhash_chevella]

Can you try with the following code?

module ICGcell(input clk, input en, output gclk)

reg l_out;

always @ (*)
begin
if(~clk)
l_out = en;
end

assign gclk = l_out & clk;

endmodule

Let me know if it works. (it will infer Latch + AND)