How do I replace 'define with regular expression in a verilog code?

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Hello everyone,

I am trying to run Synopsys Primetime but it does not support the 'define macro. My code includes following instructions.

`define DW_npp ((a_width/2) + 2)
`define DW_xdim (a_width+b_width+1)
`define DW_bsxt (a_width+1)

How can get rid of these macros without affecting the operation of code? can I replace these 'define macros with regular expression?

Any help and examples would be appreciated.
 

I don't get why you still have defines in your netlist. Primetime takes a gate level netlist, sdc, and sdf as inputs. Your netlist should have been run through synthesis, which would have done away with all the defines.

Regardless I think you would still have problems with the a_width and b_width definitions along with the + and 1 if you perform a substitution. None of those have been synthesized to gate level.

In behavioral code where ever a define macro is located is directly substituted with the value, so yes you could use a regular expression to replace all the instances of the macro.
 

Doing preprocessing with regexes will get painful real fast. Better to use a verilog preprocessor that you can run separately from the rest of the design flow. I think Icarus verilog is a reasonable match for this type of job.

See https://iverilog.wikia.com/wiki/Iverilog_Flags , the bit under "Preprocessor Flags".
 

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