logic [1:0] s_states, s_states_next;
localparam [1:0]
S0 = 0, S1 = 1, S2 = 2, S3 = 3;
always_ff @(posedge i_clk, negedge i_rsn)
if (i_rsn == 1'b0)
s_states <= S0;
else
s_states <= s_states_next;
always_comb
begin
s_states_next = s_states;
o_match = '0;
case (s_states)
S0: if (i_bit == 1'b1)
s_states_next = S1;
S1: if (i_bit == 1'b1)
s_states_next = S2;
else
s_states_next = S0;
S2: if (i_bit == 1'b0)
s_states_next = S3;
else
s_states_next = S0;
S3: begin
o_match = '1;
if (i_bit == 1'b1)
s_states_next = S1;
else
s_states_next = S0;
end
default:
s_states_next = S0;
endcase
end
endmodule