Hello !
I've got a problem because I was asked to draw what synthezis dropped like in the picture using logic gates and D-flip/flop with set/reset.
I tried to draw this :
I tried to draw this but it didn't have sense.
But at the end I've got like reset in multiplexer and reset in D-flipflop.
How do I interpret the "if else" command ? It is not a multiplexer I guess ?
I know that multiplexer looked like that after the yosys synthesiz :
The alu design is comprised of arithmetic expressions and a mux4 (case construct). Synthesis decomposes it in elementary AND, OR, XOR and NOT operations. The choice of logic primitives is somehow arbitrary, XOR could be further decomposed. It's effectively impossible to read the original logic function from the decomposed gate level presentation or to easily check the correctness.
I wonder what you want to achieve? As mentioned before, synthesis is usually targeting to a specific hardware. It decides about availability of primitives, e.g. simple logic gates versus look-up-tables.
The alu design is comprised of arithmetic expressions and a mux4 (case construct). Synthesis decomposes it in elementary AND, OR, XOR and NOT operations. The choice of logic primitives is somehow arbitrary, XOR could be further decomposed. It's effectively impossible to read the original logic function from the decomposed gate level presentation or to easily check the correctness.
I wonder what you want to achieve? As mentioned before, synthesis is usually targeting to a specific hardware. It decides about availability of primitives, e.g. simple logic gates versus look-up-tables.
What I want to achive is that there is no consistency in interpreting the synthezis code. It should be onesided what the synthezis shows.
In Which the synthezis in my opinion should show how to use Basic Gates to create the whole logic circuit.
But after using always_ff the yosys synthezis only gave me "if" statements. I don't know Which Basic logic Gates I should use to create something.
In always combo when I used "case" I knew I was creating multiplexera and the synthezis showed me Which Basic Gates to use and how to connect them.
In always_comb I have created short multiplexera with "if(i_e)" and this is connected into always_ff. But the synthezis gave me only "if(i_e)" I don't know anymore what it is. What Basic Gates I have to use to make this logic circuit. I see only if statements in the synthezis.
I only want to know why the synthezis gave me only if statements for the multiplexer, how can I make it without any information of Which Basic logic Gates to use.
In always_comb without always_ff I had everything ( which Basic logic Gates to use how to connect them etc in the synthezis). After using always_ff I don't have any information of Which logic Gates to use To create multiplexer. I only have if statement.
Please tell me if you understand what I am asking. If not I will try to Ask it differently. I really need a help understanding it. I want to re create that circuit using the synthezis data but I have no information from the synt
ezis only if statement. And I don't know Which Gates to use, how to connect everything. I have nothing.
That's very important to me and I have no one to tell me how it works. Please and thank you.
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Selected features and typical applications:
Process almost any synthesizable Verilog-2005 design
Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog/ etc.
Built-in formal methods for checking properties and equivalence
Mapping to ASIC standard cell libraries (in Liberty File Format)
Mapping to Xilinx 7-Series and Lattice iCE40 and ECP5 FPGAs
Foundation and/or front-end for custom flows
You aren't having Yosys convert the input code to a structural netlist in a specific technology, but are instead just converting to a simplified RTL Verilog netlist.
Hence you aren't going to see "gates" just simple RTL structures that pretty much match the original code with different names.
If you don't understand how a multiplexer is implemented in gates, then take a look at the logic diagram of the truth table of a TI SN54157.
You aren't having Yosys convert the input code to a structural netlist in a specific technology, but are instead just converting to a simplified RTL Verilog netlist.
Hence you aren't going to see "gates" just simple RTL structures that pretty much match the original code with different names.
Oh so that's how it works.
But sometimes I did get a specific "gates" to recreate a multiplexer like in my post #1. That was a great example of how yosys gave me a specific convertion from a code to => specific gates with specific connections. And I was really shocked when I saw the RTL/Yosys convertion of always_ff block, in which didn't give me a specific gates with specific connections like with always_comb RTL/Yosys but instead I got "if" statements that was something like multiplexer but weren't them + there were no connections of this multiplexer to other stuff. There was only connection from input, the output of the multiplexer connected to D flipflop was completelly ignored by the RTL, I don't know why, because there are two different gates multiplexer output to input D flipflop but there is no connection in the RTL.
Sorry for overcomplicating it I am just a bit new to this plus this is less intuitive.
They are equivelant, but I am trying to understand how to recreate the whole circuit using logic gates. From always_ff I don't know but from always_comb I know because it has every gates + every connections. In other hand from always_ff I don't have anything but "if" statements, even the input i_e which is in always_comb was written in RTL as "if" statement which was something like multiplexer but the output was already o_y and there wasn't any "inside" connection between multiplexer and D flipflop, I don't know why RTL ignored it.
Oh so that's how it works.
But sometimes I did get a specific "gates" to recreate a multiplexer like in my post #1. That was a great example of how yosys gave me a specific convertion from a code to => specific gates with specific connections. And I was really shocked when I saw the RTL/Yosys convertion of always_ff block, in which didn't give me a specific gates with specific connections like with always_comb RTL/Yosys but instead I got "if" statements that was something like multiplexer but weren't them + there were no connections of this multiplexer to other stuff. There was only connection from input, the output of the multiplexer connected to D flipflop was completelly ignored by the RTL, I don't know why, because there are two different gates multiplexer output to input D flipflop but there is no connection in the RTL.
You have NEVER had output that is a gate level netlist from Yosys. The "gate" file you mention from post #1 is an HDL file full of assign statements with Verilog statements representing logic operations on various signals. That is not a gate level representation of the design. A gate level RTL file will have no Verilog assigns, no always blocks, it will be made up entirely of instantiated modules from a technology library.
You have NEVER had output that is a gate level netlist from Yosys. The "gate" file you mention from post #1 is an HDL file full of assign statements with Verilog statements representing logic operations on various signals. That is not a gate level representation of the design. A gate level RTL file will have no Verilog assigns, no always blocks, it will be made up entirely of instantiated modules from a technology library.
Your first picture, right side, is not a gate level netlist, it is a Verilog HDL file that has assign statements that represent the gate level logic that could be used to translate into a gate level netlist.
Your first picture, right side, is not a gate level netlist, it is a Verilog HDL file that has assign statements that represent the gate level logic that could be used to translate into a gate level netlist.
For if(i_e) the RTL hasn't changed it into gate level logic representation ? I know that for always_ff it must be if/else statements but if(i_e) is not in always_ff hence it can be represented the same way as the first picture with gate level logic, but it didn't. I'll try to force it but I don't know why it didn't do it at the first place.
Gate level looks like the examples here. The code you have has stuff like assign _00_ = ~i_a[0]; which may represent the same thing as not u_not (_00_, i_a[0]); but is still just HDL code.
The not above is a Verilog builtin gate primitive, but if you supply a vendor gate library to a synthesis tool it might give a result with a different cell name, e.g. from the Oklahoma State University library for TSMC018 INVX1 you would have the line INVX1 u_invert (.Y(_00_), .A(i_a[0])); instead.
Gate level netlists don't have anything but cells from a library.
I've got another question which refers to the past one but cannot comment it again. I've got more precise question this time.
I'll show two different situations.
1.
2.
In picture nr.1 don't mind the note about how to draw it.
I want some confirmations for those statements :
- in the 2nd picture "case" statement works as a multiplexer here and the "if" statement works as a flag.
- in the 1st picture "if" statement in always_ff works as DFF - D Flip flip, and the "if" statement in always_comb is not a DFF.
Questions :
- Why the "if" statement in 1st picture in always_comb is treated as Multiplexer ?
- Why the Sythensiz from 1st picture doesn't have any assigments like it was in 2nd picture. Both of them have multiplexer but only 2nd picture have assigments and the 1st one doesn't, why ?
- How to interpret any "if" statement in 1st picture if (let's assume) I didn't have the original code ? How to know which one of them is multiplexer and which one is not. In the 2nd picture it is somehow recognisable when you connect every connection like _1_, _2_ etc and the multiplexer there is a "case" statement.
Side notes :
I don't know for which family it is maybe FPGA ? Why do I use such assumptions ? Because I didn't have any options to choose I just wrote the code on SystemVerilog using IcarusVerilog and synthesized it with Yosys. All of it using Visual Studio Code. It didn't require for me to choose the family
Here is the code I use to sythezise verilog codes :
# Utworzenie kopi modulu z inna nazwa
copy top_module top_module_rtl
# Ustawienie hierarchii projektu na nowy modul
hierarchy -top top_module_rtl
# Synteza logiczna
synth
# Mapowanie na bramki
abc -g AND,OR,XOR
# Optymalizacja po mapowaniu
opt_clean
# Zapis wyniku symulacji
write_verilog -noattr top_module_rtl.sv
# Wypisanie statystyki uzytych bramek
stat -tech cmos
Wanted to reanimate the question because I came back doing again SystemVerilog stuff.
And this question hits me again because I stumbled into similar if not the same situation.
I don't understand when "if" statement is interpreted as : 1. Multiplexer, 2 as DFF or 3. As a flag.
Copying the questions
Questions :
- Why the "if" statement in 1st picture in always_comb is treated as Multiplexer ?
- Why the Sythensiz from 1st picture doesn't have any assigments like it was in 2nd picture. Both of them have multiplexer but only 2nd picture have assigments and the 1st one doesn't, why ?
- How to interpret any "if" statement in 1st picture if (let's assume) I didn't have the original code ? How to know which one of them is multiplexer and which one is not. In the 2nd picture it is somehow recognisable when you connect every connection like _1_, _2_ etc and the multiplexer there is a "case" statement.
Side note : why multiplexer have different Synthesis ? It should be similar as far as I know because it is multiplexer but first picture has no assignments which is weird because looking at second picture where multiplexer had many assignments that showed how to connect each netlist to logic gates in which in the first picture there are none assignments but it has also the multiplexer i've assumed the multiplexer will have assignments or that Synthesis usually have assignments. Why is it like that ?
I wonder what you want to achieve? As mentioned before, synthesis is usually targeting to a specific hardware. It decides about availability of primitives, e.g. simple logic gates versus look-up-tables.
To answer this old question while finding the answer might be one.
I am learning the SystemVerilog and so I didn't understand why it gave me different solutions.
Teacher said that Yosys that is for Synthesis should give the most simple version of what was written using logic gates. In second picture it was crystal clear it used logic gates. In first picture it is not because there are no assignments althought there was always_comb. My thing was there were two multiplexers but differently written why. And why there is no assignments. This is pretty illogical because the Yosys was set to use logic gates although It gave something else.
What hardware it was targeting ? I don't know. If I knew I would say because I simply write the code in Verilog and synthesize it with Yosys. I don't pick a specific hardware, or so there is no way to pick a hardware.
What do you think ?
I know you knew something about these stuff, although I still don't get it. Thus I wanted to understand this in a conctext of why it didn't do assignments for multiplexer in picture nr. 1 but it did assignments in picture nr.2 even though both of them used multiplexer so where is the logic in it ? That the same multiplexer is written differently even though they behave the same. I thought it would make assignments for the first picture as well but it didn't why though.
I believe the question has been already discussed.
I expect that you have different tool settings for both codes. Picture 1 is simply translating System Verilog to plain Verilog. Picture 2 is translating to logic primitives (and, or, not). It's not actually synthesis because no hardware target is defined, the point has been extensively explained by ads-ee.
I believe the question has been already discussed.
I expect that you have different tool settings for both codes. Picture 1 is simply translating System Verilog to plain Verilog. Picture 2 is translating to logic primitives (and, or, not). It's not actually synthesis because no hardware target is defined, the point has been extensively explained by ads-ee.
What if I say both pictures are from the same Yosys ?
I can send what I have in the file that Yosys uses :
run.ys - run yosys
Code:
# Wczytanie pliku modelu
read_verilog -sv comparation.sv
# Utworzenie kopi modulu z inna nazwa
copy comparation comparation_rtl
# Ustawienie hierarchii projektu na nowy modul
hierarchy -top comparation_rtl
# Synteza logiczna
synth
# Mapowanie na bramki
abc -g AND,OR,XOR
# Optymalizacja po mapowaniu
opt_clean
# Zapis wyniku symulacji
write_verilog -noattr comparation_rtl.sv
# Wypisanie statystyki uzytych bramek
stat -tech cmos
And a makefile
Code:
EXAMPLE = comparation
rtl:
# Uruchomienie syntezy yosys
yosys -s run.ys | tee synth.log
sim: compile
# Wykonanie skompilowanego programu symulacji
./${EXAMPLE}.iveri.run
compile: clear
# Kompilacja modulow verilog do programu wykonywalnego
iverilog -g2005-sv \
*.sv \
-o ${EXAMPLE}.iveri.run \
| tee ${EXAMPLE}.iveri.log
waves:
# Uruchomienie przegladarki przebiegow GTKWave
gtkwave signals.vcd &
clear:
# Usuwanie wyniku kompilacji Icarus Verilog
if [ -f ${EXAMPLE}.iveri.run ] ; \
then rm ${EXAMPLE}.iveri.run ; fi
It was for Comparation module in SystemVerilog that's why it is comparation in those codes.
So I didn't choose any device in writing it thus I don't know where is that option to choose.
More importantly you said that it is not synthesis. So what is Yosys ? And why Yosys did give me those 2 different results from each other. In which for case nr.1 it was like you said From system verilog to Verilog and for picture nr.2 from System verilog to logic primitives.
Why it choosed two different ways to translate it like you've said using the same program Yosys. In both there is multiplexer but in the 1st picture the multiplexer still is left with "if" statement and in picture nr.2 it is decomposed into primitive logic. I don't understand why Yosys did that.
And yes the case was extensively explained by ads-ee but it didn't fully answer my question/it didn't answer the question of why yosys gave two different answers to the same multiplexer (one multiplexer with cases has like 3 options and one multiplexer with "if" but only 2 cases). The confusion is that it is multiplexer no matter if it's case or "if" statement it is a multiplexer but decided to use two different approach. Why ? Just because ? Why it didn't use the simple logic primitives like in picture nr.2
Like I've mentioned above I don't know what else I could change ;D So it was basically the same but yosys returned two different outputs which I've called synthesis because yosys is na RTL synthesis, so the picture nr 1 and 2 the right side are the yosys outputs so they are the synthesis but you've said they are not.
What the real synthesis looks like if mine from the Yosys are not ? And why in god sake for the same multiplexer it gives two different codes when I haven't changed a thing
@FvM
I don't want to be a burden but I can't let it go not understanding it ;>
Like why it gave me two different results when I gave the same makefile and run.ys file. Which is weird and you've mentioned it is not synthesis although the output is from yosys ;>
I think, there's no specific reason why the tool produces different logic representation for combinatorial versus registered input. Even if it's a default behavior of the tool for some reason, it should be possible to switch the output format according to your needs. Read the tool manual and try different options.