How do I interpret "if" statement in different always_comb situations ?

[Xenon02]

Hello !
I've got a problem because I was asked to draw what synthezis dropped like in the picture using logic gates and D-flip/flop with set/reset.

I tried to draw this :

I tried to draw this but it didn't have sense.

But at the end I've got like reset in multiplexer and reset in D-flipflop.
How do I interpret the "if else" command ? It is not a multiplexer I guess ?

I know that multiplexer looked like that after the yosys synthesiz :

 

[FvM]

FF with asynchronous reset and clock enable, respectively input mux.

 

[Xenon02]

FF with asynchronous reset and clock enable, respectively input mux.

View attachment 180603

So how do I understand this "if" in verilog ?

Also multiplexer looked different like this :

So why now the multiplexer is the "if" ?
Like one time the multiplexer is "if" and one time it is something like this :

 

[FvM]

There's no simple one-to-one correspondence between single behavioral statement and structural description. You need to analyze the context. In case of the FF with clock enable, you have an implicit else that holds the previous state. The clock enable can be emulated by a mux.

 

[Xenon02]

There's no simple one-to-one correspondence between single behavioral statement and structural description. You need to analyze the context. In case of the FF with clock enable, you have an implicit else that holds the previous state. The clock enable can be emulated by a mux.

I thought that verilog is more simple to interpret the code.
What do I mean is : case = multiplexer so it's synthezis will show me how the gates must be connected. In the case of the FF it looks like there is "if" which works like multiplexer or this "if" works like D-flipflop but what gates should I use it should show me which gates to use I guess ? Synthezis should say which gates should I use and how do I connect them I guess.
Here I see only "if" and I don't know how to connect them.

I don't know I don't understand this.
It's hard to say what do I mean, but maybe you can understand me

 

[Xenon02]

@FvM
What do you think about my post ?
I mean I don't get it why in once situation "case means multiplexer and it has many logic gates, and in other cases "if" is the multiplexer, and there aren't any logic gates". I know that Synthezis should show how to connect logic gates so if one times "if" is as multiplexer and once as D flipflop so how the program knows which to use to create the circuit ? There is only D flipflop, there are no AND, OR, XOR gates so how does the program know how to do D flipflop if the synthezis didn't show to co create the D flipflop using simple gates.

 

[FvM]

DFF is generated for each output bit of clocked always block (always_ff in your example). Combinational logic is generated for combinational and clocked blocks according to the logic expressions, no matter how they are described, e.g. logic operators, conditional code (if .. else), case construct, whatsoever. You need to decode the logic, e.g. write a truth table to see the final logic function.

 

[Xenon02]

DFF is generated for each output bit of clocked always block (always_ff in your example). Combinational logic is generated for combinational and clocked blocks according to the logic expressions, no matter how they are described, e.g. logic operators, conditional code (if .. else), case construct, whatsoever. You need to decode the logic, e.g. write a truth table to see the final logic function.

I don't get it could you explain it again ?
When I make multiplexer with always_comb I get AND,OR,NOR,XOR etc. and this tells me how to create a certain circuit using these gates and how to connect them.
For always_ff I can also create multiplexer but it uses "if" which is both for D flipflop and for multiplexer so how can I and the program know which is which ? Moreover it is only written that is uses "if/else" so how do we know which basic logic gates to use to create D flipflop or multiplexer ? I am a bit confused.

--- Updated Jan 7, 2023 ---

@FvM
I mean it's hard to say what do I mean. It's so wierd to know what the program understand these "if/else" when they can mean whether multiplexer or D flipflop and these if else doesn't have any logic gates connection in the synthesiz. So how do I know and how does the program know which part of the logic gates to connect for it to work when there is no logic gates only "if/else".

--- Updated Jan 7, 2023 ---

PS.
Sorry for asking, but how does the program know where to connect this output of this multiplexer to D flipflop ? It is for s_x but there is no s_x after synthesiz after the multiplexer the i_x is automatically applied to o_y, so I don't know if it's okey.

 

[FvM]

clocked always block creates DFF, not the if statement. if statement is used to describe reset function and possibly clocke enable.

// simple DFF
always_ff @(posedge clk)
   q <= d;

// DFF with asynchronous reset
always_ff @(posedge clk, posedge reset)
   if (reset)
     q <= 1'b0;
   else
     q <= d;

// DFF with asynchronous reset and clock enable
always_ff @(posedge clk, posedge reset)
   if (reset)
     q <= 1'b0;
   else if (enable)
     q <= d;

 

[Xenon02]

clocked always block creates DFF, not the if statement. if statement is used to describe reset function and possibly clocke enable.

// simple DFF
always_ff @(posedge clk)
   q <= d;

// DFF with asynchronous reset
always_ff @(posedge clk, posedge reset)
   if (reset)
     q <= 1'b0;
   else
     q <= d;

// DFF with asynchronous reset and clock enable
always_ff @(posedge clk, posedge reset)
   if (reset)
     q <= 1'b0;
   else if (enable)
     q <= d;

Okey so if/else is to create DFF - as I understand this is a shortcut for D flipflop.
But in my code there is i_c as a clock, i_r as a reset and something i_e which is not a clock. But this i_e is in another "if" statement. So it creates not a multiplexer but a D flipflop ? If so then why did you write second "if" as a multiplexer when "if" statement creates DFF.

Additional question what does "if" means in always_comb ? How do I write it in logic gates ?

 

[FvM]

i_e corresponds to enable in my example. I already explained how clock enable is emulated by a mux.

 

[Xenon02]

i_e corresponds to enable in my example. I already explained how clock enable is emulated by a mux.

Oooh so if I add more "if" statements in always_ff then I can have more clock enable ? so it is multiplexer connected to multiplexer ?
I do have one more question.
If it's a multiplexer then why doesn't it have any logic gates like it was with always_comb multiplexer version ?
Because all it is written is if(i_e) <instruction>. How does the program that makes circuits that this if is a multiplexer and must be made out if specific logic gates (some XOR,OR AND etc.) Because in always_comb I know how to make multiplexer based on the synthezis that shows which gates to use. And the example with this it i_e it says that i need 4 DFF and it doesn't say anything about Multiplexer (yosys logs).

 

[Xenon02]

@FvM
You know what do I mean ?
It's hard to say it but maybe this approach will work ? : Always_comb multiplexer tells me which logic gates use (AND,OR,XOR etc.), always_ff only uses DFF, and when I see that there is "i_e" which is know for clock enable and it is interpreted also as a multiplexer, but in the synthezis it shows only that there is "if" like how to connect them ? There are no (AND,OR, XOR) only "if" for multiplexer, so how do I know or other programs how to make this multiplexer only from "if" statement ?
Here it is said how to construct multiplexer :

On the right side is the synthezis, so that's how I need to make this multiplexer, using (AND XOR OR etc.)
Here :

I dont really mych know because there is only "if". So how do I know how to build this multiplexer ? It looks like I need to use 4 DFF in total. In synthezis logs I think it shows the same that I need to use 4 DFF there is no multiplexer mentioned. So I am a bit confused.

But I get it that i_e is a multiplexer of what you said but this synthezis doesn't provide any information about it plus there is no information how to make this multiplexer.

 

[FvM]

Not yet mentioned in your thread, which hardware are you synthesizing? If it's FPGA, most families have logic elements comprised of configurable 4 to 6 input LUT (look-up table) implementing the combinational logic, a DFF with different features (e.g. reset, possibly set, possibly dedicated clock enable) and static routing muxes.

Most synthesis tools can visualize both RTL and finally synthesized netlist. I was drawing the clock enable mux in post #2 because you only offered a basic DFF. The actual FPGA implementation may look different if the LE has a DFF with clock enable.

 

[danadakk]

A handy tool : http://digitaljs.tilk.eu/#

Regards, Dana.

 

[Xenon02]

Not yet mentioned in your thread, which hardware are you synthesizing? If it's FPGA, most families have logic elements comprised of configurable 4 to 6 input LUT (look-up table) implementing the combinational logic, a DFF with different features (e.g. reset, possibly set, possibly dedicated clock enable) and static routing muxes.

Most synthesis tools can visualize both RTL and finally synthesized netlist. I was drawing the clock enable mux in post #2 because you only offered a basic DFF. The actual FPGA implementation may look different if the LE has a DFF with clock enable.

I think it is FPGA ?
I am actually using SystemVerilog and Yosys (for synthesiz).

So for example this module :

module alu(i_a, i_b, i_oper, o_y, o_zero);
parameter WIDTH = 2;
input logic [WIDTH-1:0] i_a, i_b;
input logic [1:0] i_oper;
output logic [WIDTH-1:0] o_y;

// Znacznik zera w wyniku
output logic o_zero;

always_comb
begin

{o_y, o_zero} = '0;

case(i_oper)
2'b00 : o_y = i_a + i_b;
2'b11 : o_y = i_a & i_b;
2'b01 : o_y = i_a - i_b;
default : o_y = 'd0;
endcase

if (~| o_y )
o_zero = '1;

end
endmodule

After synthezis (Yosys) :

/* Generated by Yosys 0.9+4292 (git sha1 UNKNOWN, gcc 11.2.1 -O2 -fexceptions -fstack-protector-strong -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fPIC -Os) */

module alu(i_a, i_b, i_oper, o_y, o_zero);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
input [1:0] i_a;
input [1:0] i_b;
input [1:0] i_oper;
output [1:0] o_y;
output o_zero;
assign _00_ = ~i_a[0];
assign _01_ = ~i_b[0];
assign _02_ = ~i_oper[0];
assign _03_ = i_a[0] | _01_;
assign _04_ = _00_ ^ i_b[0];
assign _05_ = i_oper[1] | _04_;
assign _06_ = i_oper[0] & i_oper[1];
assign _07_ = i_a[0] & i_b[0];
assign _08_ = _06_ & _07_;
assign _09_ = ~_08_;
assign _10_ = _05_ & _09_;
assign o_y[0] = ~_10_;
assign _11_ = i_b[1] & i_a[1];
assign _12_ = _06_ & _11_;
assign _13_ = ~_12_;
assign _14_ = _02_ | i_oper[1];
assign _15_ = i_b[0] & _14_;
assign _16_ = i_b[1] ^ i_a[1];
assign _17_ = _15_ ^ _16_;
assign _18_ = _03_ ^ _17_;
assign _19_ = i_oper[1] | _18_;
assign _20_ = _13_ & _19_;
assign o_y[1] = ~_20_;
assign o_zero = _10_ & _20_;
endmodule

I can see how to connect every bit with any logic gate so I know that the program also know how to connect them. And I can see that it is a multiplexer

the program made it a bit wierdly like I don't see in the program any multiplexer, but all of it is one huge multiplexer.

I am a bit confused.

Here (I only have a screen shot) :

Left side is before synthezis and the right side is after syhtezis.
Also good to note that "if (i_e)" is not in always_ff but it is in always_comb, so it should give me an logic gates but it didn't.
My confusion is that the same multiplexer looks wierd for me to interpret from synthezis from always_ff.
I mean I know how to connect which input to which output and where to connect the output to the next input. Here I see if(i_e = 1) then o_y[1] = i_x[1] but this is a multiplexer ! There should be a connection between multiplexer and DFF like s_x but there is not. Like here :

But there is no name for the connection multiplexer - DFF because synthezis got rid of s_x.
Overall, I don't get it how in one application always_comb the multiplexer is very intuitive and I know how to connect logic gates (Or,AND,XOR ) to create this multiplexer, and the program also sees the logics gates and know how to connect them.
Multiplexer in always_ff is tricky, because all I see in the synthezis is ("if") which if(i_e) is in always_comb. But there is no logic gates (XOR,OR,NOR,AND), so how does he know how to create multiplexer ? In the always_comb he had a instruction how to create multiplexer, here in always_ff he doesn't. Also there is one connecton MUX - DFF that doesn't exist.

 

[FvM]

I don't understand how you synthesize FPGA hardware without specifying a FPGA family.

 

[Xenon02]

I don't understand how you synthesize FPGA hardware without specifying a FPGA family.

I wasn't sure exactly.
I just use Yosys and SystemVerilog and they said it is something related to FPGA.
So that's why I am confused on how programs interpret what I see in the synthesiz, that one time multiplexer looks like basic gates connected to each other and one time on always_ff multiplexer is differently written and doesn't consist any information which basic gates it uses, there is only ("if") in the synthesiz also there is no information how output of the multiplexer is connected to the input of DFF there is no information at all.

 

[FvM]

Left side is before synthezis and the right side is after syhtezis.

I won't name the operation synthesis. Left and right side are functionally equivalent, it's just reordering of Verilog code. I realize that you don't understand how different Verilog text can represent the same logic function. I don't feel able to explain it within this thread.

 

[Xenon02]

I won't name the operation synthesis. Left and right side are functionally equivalent, it's just reordering of Verilog code. I realize that you don't understand how different Verilog text can represent the same logic function. I don't feel able to explain it within this thread.

Please ;( I really don't know where to find this answer.
I know that left and right side are equivelant.
Okey again look at this :

This is one big multiplexer it looks like that :

The synthezis says how to connect them to look like this multiplexer. I am right yes ?It says which gates to use like i_oper[1] and _18_ are connected to the gate OR. So I know how to build this multiplexer.

Here :

What I sign in red is also a multiplexer but in always_ff. But there is no information how to make this multiplexer there is only "if". I don't know which logic gate to use I don't know if I should use OR gate or AND gate or XOR gate or any other basis gates.


But both of these codes make this multiplexer, and I don't get it. How I know this is a multiplexer or rather how to make it when there is no information which gates to use and how does the program know it ?