how do i implements this design

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Hi,guys!
Given a clock signal clk,and a pluse signal which may be short or long,so how do i generate a new pluse which hold high level at least for a cycle of clk???Can i.give any suggestion pelease??
 

ur english is very confusing (no offense, since wrong punctuation, spelling mistake and mix of words that making difficult it to understand). But i will try to answer from whatever i understood. According to post, u want to make frequency divider by 2 i.e. o/p freq divide is i/p freq/2:
1. use this circuit to decrease the frequency by half: be sure to have not gate delay as low as possible.

2. use T-Flip-Flop and give the clock signal u have as clock input to this flip flop, the output will be input freq/2.

Hope that helps.
 

First, sorry to my bad english!
Then,it's like this!
Actually,i want to design a SPI master module,and make it as a periphel of a 51 cpu core,they communicate through APB3,
but i want the SPI use a external clock source not cpu CLK,then how SPI can i know when want it to send the data?
SPI external clock source is not relevant to CPU CLK!
 

as far as i understand the question:
1. u can't use external clock for SPI, according to SPI architecture, only master will provide the clock for slave to sync the data and communicate. U have to reply on master SPI clock. But why do u want external clock for SPI?
2. As u mentioned at first, u can have external SPI master peripheral device and have I2C or RS232 communication between SPI master and 8051. Im not much aware of APB3 interface. But still, why do u need external SPI Master when 8051 SOC can give u its own internal SPI master peripheral?

If u dont use SPI clock of master device, the master won't be able to sync with slave, u have to use SPI master generated clock to communicate to slave device.

Hope that helps.
 

You'll have to design an interface (usually through a FiFo) to communicate with your ARM APB3 interface. Do you actually want to implement a C51 core with an APB3 interface?

The SPI master needs to generate the clock signal for the SPI slaves. This SPI clock may be generated as a derivate of a system clock. One way (that I have implemented in the past) uses a state machine, but there might be other ways that better fit your needs.


SPI external clock source is not relevant to CPU CLK!
Click to expand...
that's true - therefore the fifo
 

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