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The best way to avoid hazards is to keep your design fully synchronous.
And introduce asynchronous signals only if you hardly need it. To avoid glitches in asynchronous part you could try to align paths of concurrent signals in such a way, that they will reach the hazardous gate at the same time. Or, you could try to change your design to avoid hazards on functional level. The excellent tutorial on this topic is available here:
**broken link removed**
But keep in mind that all this stuff will work ONLY if one signal could be changed at the same time. Otherwise, even the simple AND (OR) gate will produce the glitch when you change its inputs from 01 to 10.
If u can access some patent database. Search the keywork de-glitch circuits, i found there are many patent about de-glitch b4.
Here's someone's crazy way to reduce the glitch ,
1. assume the layout trace to the input is unknow and probaly to be distributed as random values between the signal paths.
2. assume the glitchs are also random distribute around the clock edge.
Then we know the theory that the correlation between random variable
is zero. So u may operate the glicth signals several time under some
boolean operator. So the random op random would make the result toward zero. That reduce glitchs less or more .
If you need a really urgent solution, put a small cap (10-100pf) from the output of the gate to the ground. A serial rezistor (10-200) at the output, before the cap would be better.
regards
Sorry
I didn't realize this was Asic design forum. Forget the above suggestion.
In case of Asics, clocking the input signals and the output signal with the same clock may produce a clean output.
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