isaac12345
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ICMR=0.8 to 3.0v @ Vdd=2.2v --- are you sure?
Show what you already have designed! Which spec didn't you meet?
Which process?
Is this a serious question, really?I think we can suppose that Vdd is 5v.Will that affect power dissipation?
Show it anyway, after you get access. Or a drawing of your design, at least.I'm stuck at the schematic simulation in cadence virtuoso. Dont have access to the computer for the next few days where the schematic is stored but safe to say its a mess of an attempt by a beginner.
Don't expect forum members to do your job. These forums are meant to help with special individual problems, if the thread starter shows what he's done before, and if he's willing to give enough info to help him.Can you post the schematic and more importantly how you went about designing it?
Sounds better.- - - Updated - - -
Jut confirmed icmr is 0.8 to 2.0 v @vdd= 2.2v
Is this a serious question, really?
Show it anyway, after you get access. Or a drawing of your design, at least.
Don't expect forum members to do your job. These forums are meant to help with special individual problems, if the thread starter shows what he's done before, and if he's willing to give enough info to help him.
Until now you didn't even respond to all the questions: which process? More exactly: which models do you use? Are you aware that the Gain Bandwidth Product (UGB) depends rather much on the load impedance? No info about this ...
Not too bad, I think ;-)How's this one? The design of CMOS differential Amplifier - Part.1
Not too bad, I think ;-)
Now here's sort of a suggestion for your diff-amp. As you didn't provide any info about your process/models/threshold voltages, I had to use my own. They're from a 0.18µm process; I assumed a load capacitance of 1pF :
View attachment 141400
Note: Presumably, your process, especially your models might be quite different from mine, so it's predictable that you'll attain rather different results. Hence consider my above suggestion just as a first trial for your design, then try and optimize to achieve your specs.
Also pls. note that my simulations are based on schematics (pre-layout), and that post-layout simulations (if you need to generate a layout) will obviously result in a considerable lower fT (gain-bandwidth product), due to parasitics.
This one: Qucs
Where did you start from?
It's a bias current. By M1 multiplied by 4 for the 2 branches.I0 is reference current?
By multiplying V0's voltage with Pr1's current value.how you measured the power dissipation?
A moderate substitute, I'd say, but free software. At least it involves a SPICE-like simulator. Problem is to integrate the models.How is the software compared to Cadence Virtuoso? Is it a decent substitute?
From your specs.2. And how did you go about designing the circuit? Where did you start from?
V1dc constitutes the ICM voltage. Stepped by a DC simulation sweep. For I0 s. above.3. What's V1dc and I0 for?
DC1 is the name of the DC simulation (for the stepped ICMR simulation).4. What's DC1 for?
It's the master of the M3->M1 current mirror.5. What's M3's function?
Study Analog Circuit Design textbooks, YouTube presentations on this stuff, and follow the thread explanations in this forum!6. How do I get good at analog electronics?
It's a bias current. By M1 multiplied by 4 for the 2 branches.
By multiplying V0's voltage with Pr1's current value. View attachment 141492
A moderate substitute, I'd say, but free software. At least it involves a SPICE-like simulator. Problem is to integrate the models.
From your specs.
V1dc constitutes the ICM voltage. Stepped by a DC simulation sweep. For I0 s. above.
DC1 is the name of the DC simulation (for the stepped ICMR simulation).
It's the master of the M3->M1 current mirror.
Study Analog Circuit Design textbooks, YouTube presentations on this stuff, and follow the thread explanations in this forum!
How did you go about deriving the various values(equations,calculations,etc)?
Experience, a few calculations (or - rather - estimations), and simulations.
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