How display an img (100 x 100) in VGA using Block ROM

Hi dear friends,

I need to display an image (100 x 100) using IP core generator (Block ROM) , with memory type single port ROM. I have Spartan 3E- CP132 family FPGA board. Now I want to learn that is this board has a enough memory to store that image data? Or Do I have to use Virtex family for that process? I have learnt that the FPGA board I have is not enough memory to store 256 x 256 image. What about 100 x 100 img? There is complex information about this information. So I have a bit confused.

By the way, I have a VGA controller and it works correctly. I know how to use IP core generator, I used that parameters below for this interface :

Memory Type : Single Port ROM
Read Width : 8
Read Depth : 10000

I also obtained .coe file for related image. And after that whenever I pushed the Generate button , I see different error problems. So what should I do ? I need your advice. Thanks dear friends.

Best Regards

hitx, you keep making posts with incomplete information. Spartan 3E parts do not have CP132 part numbers that is a package type which tell us nothing about the size of the part. The very first datasheet that comes up on Xilinx's website for the Spartan 3E shows the number of BRAMs in the part.
https://www.xilinx.com/support/documentation/spartan-3e.htm
Spartan 3E parts have 18Kb BRAMs

So what should I do ?

Click to expand...

As you never supply useful information in your posts it's impossible to help you with your .coe problem. Maybe posting your error and the first 10 and last 10 lines of the coe file might help.

100x100 monochrome? Or 24-bit colour? Just multiply the number of bits per pixel by the number of pixels, and compare that to the size of the block memory resources available in your device to get a rough idea about if your FPGA is large enough. In practice because block ROM has a fixed width (e.g. 36 bits) you might want to consider how you pack the data. If you're using 24 bits per pixel and there's enough BRAM to do so, you might just waste the additional 12 bits (36-24) to make your logic easier.

I have a Spartan 3E - XC3S100E CP132 fpga board. I have checked the datasheet of my fpga, It is defined as, it has 4 Block RAMs, each of them is 18 K, so total RAM is 72 K which gives us 72*1024 = 73728 bits. I know that FPGA uses 8 bits per pixel, if I am not wrong. So when I use 100 x 100 image to store its data, I need 100x100x8 =80000 total bits which is not enough to store under this condition. Until now, Am I right?

By the way, I will use Xilinx ISE, IP core generator. For this purpose, Do I need to select Single port ROM or Single Port RAM. And what sould be the other values :

Read Width : 8
Read Depth : 10000

I am not sure these values are correct or not for my situation. Please help. Thanks friends.

hitx said:

I have a Spartan 3E - XC3S100E CP132 fpga board. I have checked the datasheet of my fpga, It is defined as, it has 4 Block RAMs, each of them is 18 K, so total RAM is 72 K which gives us 72*1024 = 73728 bits. I know that FPGA uses 8 bits per pixel, if I am not wrong. So when I use 100 x 100 image to store its data, I need 100x100x8 =80000 total bits which is not enough to store under this condition. Until now, Am I right?

Click to expand...

Sounds right.

By the way, I will use Xilinx ISE, IP core generator. For this purpose, Do I need to select Single port ROM or Single Port RAM. And what sould be the other values :

Click to expand...

The rom vs ram should be evident. If you want a static picture you can use rom, if you actually want to make changes to your image you use ram. And should you be doing updates, you may want to look into using dual port ram. Not that you use it per se, but just check if it helps meet your requirements. Dual port can be handy for this sorts of thing.

hitx said:

I have a Spartan 3E - XC3S100E CP132 fpga board. I have checked the datasheet of my fpga, It is defined as, it has 4 Block RAMs, each of them is 18 K, so total RAM is 72 K which gives us 72*1024 = 73728 bits. I know that FPGA uses 8 bits per pixel, if I am not wrong. So when I use 100 x 100 image to store its data, I need 100x100x8 =80000 total bits which is not enough to store under this condition. Until now, Am I right?

Click to expand...

Sounds right, but you'll be forced to use distributed ram (registers will use up even more resources) to store the rest of the bits 80000-73728=6272 or 6272/16=392 LUTs. You're going to have to deal with a lot of alignment problems with the data being 8-bits but the memory having 9/18/36 widths. The 36 width is the easiest to work with as you'll have only two cases to deal with:

b[0][7:0], b[1][7:0], b[2][7:0], b[3][7:0], b[4][7:4]
b[4][3:0], b[5][7:0], b[6][7:0], b[7][7:0], b[8][7:0]

If you don't do something like this you'll waste a lot of the bits available in the block rams. You should really use whatever external memory is supplied on the board you are using to store the image, then you could actually store a 256x256 image. FYI FPGAs make poor storage buffers.

hitx said:

I know that FPGA uses 8 bits per pixel, if I am not wrong.

Click to expand...

An FPGA doesn't have any concept of pixels or colour depth. Your development board might have a VGA output that limits the colour depth, though. If it's truly 8 bits, you might have three bits of red, three of green, and two of blue, or something like that. If it uses DACs you might be able to use 8-bits each of red, green, and blue.. which will require 24 bits of data per pixel. Of course you don't have to use the full resolution of the video output port if this helps you to conserve your memory resources.