cherishnguyen
Newbie level 5
Hi all,
I have read through some doc about ADPLL. It containts 3 parts: PFD, Filter, DCO. The main part DCO will adjust the output based on input frequency. Let say: i want to generate output fo= 2fi from reference input freq, fi= 100Mhz. The DCO will do some stuff in order to generate fDCO=200Mhz, and in this state, fDCO = fo, we call it "PLL Locked". This can easily done by using a counter or accummulator in DCO. BUT i wonder about the phase difference between 2 signal fDCO, and fi. It's seem to me that ADPLL easily say "PLL Locked" when 2 signals equal (frequency equality) , and don't care about the phase between them, early or lately.
Can anyone help me out? what really means by that word "locked"? Since, some docs i have read about DDS just only focus on what argorithm to get fDCO ~ fo, and nothing concern about phase difference, even they used the Phase Frequency Dectector.
I have read through some doc about ADPLL. It containts 3 parts: PFD, Filter, DCO. The main part DCO will adjust the output based on input frequency. Let say: i want to generate output fo= 2fi from reference input freq, fi= 100Mhz. The DCO will do some stuff in order to generate fDCO=200Mhz, and in this state, fDCO = fo, we call it "PLL Locked". This can easily done by using a counter or accummulator in DCO. BUT i wonder about the phase difference between 2 signal fDCO, and fi. It's seem to me that ADPLL easily say "PLL Locked" when 2 signals equal (frequency equality) , and don't care about the phase between them, early or lately.
Can anyone help me out? what really means by that word "locked"? Since, some docs i have read about DDS just only focus on what argorithm to get fDCO ~ fo, and nothing concern about phase difference, even they used the Phase Frequency Dectector.