rajavel.rv
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Hi Friends,
How i can generated a IP core from my own VHDL. I have one option Synthesis my VHDL code and get the .ngc file but its only using for ISE synthesis and simulation. But i want to generate a core for simulation in Modelsim. Anybody have a idea please help me.
How i can generated a IP core from my own VHDL. I have one option Synthesis my VHDL code and get the .ngc file but its only using for ISE synthesis and simulation. But i want to generate a core for simulation in Modelsim. Anybody have a idea please help me.