[SOLVED] How could I calculate the maximum frequency?

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u24c02

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Hi.

I didn't quite catch the following posting's answer from other people.
How could I calculate this questions?
Would you please let me know?


Given the above design,reference the figure
1.What are the effective setup and hold times between IN and CLK in the above circuit?

A. Tsetup = 4 ns, Thold = 1 ns
B. Tsetup = 3 ns, Thold = 0 ns
C. Tsetup = 3 ns, Thold = 1ns
D. Tsetup = 2 ns, Thold = 0 ns

2.What is the maximum operating frequency of the above circuit?

A. 250 MHz
B. 80 MHz
C. 125 MHz
D. 166.7 MHz
 


1. The setup/hold time are timing of the FF itself and has nothing to do with any external combinational logic. Ask yourself what is the setup-to-hold window? (setup is the time required before the clock where data must be stable and hold time is the required time after the clock where data must be stable) If you can answer that then there is only one answer that has the same exact setup-to-hold window. Latency of the data or clock input may shift the clock edge within the setup-to-hold window, but won't change the window width.

2. A
I'm too tired of answering with long winded explanations. And yeah I know it's your homework.
 

I don't want to just answer. I have already know the just answer. But Important thing is that I want to know how do I calculate at these problems.

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Yes I know the setup and hold time..Did you mean that only the xorr's delay affect on setup and hold? I didn't quite catch your answer.
 

Code: 
[FONT=Courier New]       ______        ______        ______ 
nCLK  |      |______|      |______|      |
           _____         _____
D     ----|_____|-------|_____|-------
          '2 ' 2'       '2 ' 2'   setup = 2 ns, hold = 2 ns
removing the clock delay of 1 ns moves the clock edge back 1 ns
removing the data back by 2 ns moves data transition back 2 ns
      ______        ______        ______ 
CLK         |______|      |______|      |
         _____         _____
IN    --|_____|-------|_____|-------
        '3  '1'       '3  '1'
[/FONT]
Data delay improves setup at the expense of hold time.
Clock delay reduces setup time and helps hold time.
so...
Tsu = Tffsu + Txor - Tinv = 2 + 2 - 1 = 3
Th = Tffh - Txor + Tinv = 2 - 2 + 1 = 1

See the for much better graphics than I'm willing to draw right now.

I only glanced at the picture (small phone screen) and didn't notice the clk->Q = 4 ns and didn't pay attention to the feed back path from Q->xor->D. So the frequency is much lower, as you have to add the path delays up along with the setup.
Tperiod = Tsu + Tcq + Txor = 2 + 4 + 2 = 8, so 1/8ns = 125 MHz. so it should have been C.
 

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The original thread here.
https://www.edaboard.com/threads/96287/

I think they have not any conclusion(solution).
So I was asking you. No offence:wink:

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Thanks for letting me. First of all.

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Thanks for attaching document.

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Thanks Sir, I got it what you said, I have a one query about skew, is there any affect by skew -1 or +1?
As I know, skew is different between clk1 and clk2. But I'm not sure whether it is affect or not to result.

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Sir, I just have some query about this answer.
Data delay improves setup at the expense of hold time.
Clock delay reduces setup time and helps hold time.

Yes until here, I understand totally.
but the following equation I didn't quite understand.
Especially why Tsu is calculated +Txor and -Tinv Also why Th is calculated -Txor +Tinv?

Tsu = Tffsu + Txor - Tinv = 2 + 2 - 1 = 3
Th = Tffh - Txor + Tinv = 2 - 2 + 1 = 1

Is this just considering data delay for

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Sir I have some query about your answers.


As I understood, Tsu is max setup ans Th is max hold.
Max setup have 2 case.
1. Clock delay
2. Data quick arriving more.

also Max hold 2 case.
1. Clock quick arriving more.
2.data delay

At 1,
Ts= Tffsu +Tinv-Txor = 2+1-2=1
At 2,
Th=Tffh-Tinv+Txor= 2-1+2= 3

Am I right?
 
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[Moved]What does t_min or t_max mean in STA?

Hi.

I want to know what does mean t_min, t_max as following figure.


Why do they are exist as two? like this t_min, t_max?
Is this just meaning t_min is data path of t_max is clock path?

Why we have to consider two things?
For hold: Min delay data path, Max delay clock path
For setup: Min delay clock path, Max delay data path
?
 
Last edited by a moderator:

Re: What does t_min or t_max mean in STA?

t_min and t_max are the minimum and maximum propagation delays of gates or nets in the figure. It's applicable to both data and clock paths.

They exist depending on different PVT corners. For eg. a fast corner will be where your Process is fast and Voltage is high and Temperature is low. And slow will be the reverse of each parameter. Refer this for a basic understanding.

The second part of your question requires a full understanding of how setup and hold delays are calculated.

You may refer to thread103506 here. The internet is full of articles on setup and hold since these are the most fundamental concepts in STA.
 

[Moved]Does anyone know what does effective setup and hold mean?

Hi.

When I was trying to solve some problem, I found like this question.
"What are the effective setup and hold times between IN and CLK?"

Does anyone know what does effective setup and hold mean?

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Does anyone know why do they have different sign parameter like this Txor, Tinv in Tsu,Th?

Tsu = Tffsu + Txor - Tinv = 2 + 2 - 1 = 3
Th = Tffh - Txor + Tinv = 2 - 2 + 1 = 1

Last one is that How I do calculate the Tsetup and Thold what if disconnected between Q and xor?

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Would you please let me know more detail about your answer?

Data delay improves setup at the expense of hold time.
Clock delay reduces setup time and helps hold time.
so...
Tsu = Tffsu + Txor - Tinv = 2 + 2 - 1 = 3
Th = Tffh - Txor + Tinv = 2 - 2 + 1 = 1

Above your description is that I didn't quite catch.
 

[Moved]Why do we STA(Prime Time) after synthesis(Design compiler)?

Hi.

I have some confused about why do we STA(Prime Time) after synthesis(Design compiler)?

As I know, the STA is static timing analysis.
But When I run Design Compiler, I got the timing report.
I think this this the same to STA.

As I know, I can get the report about total negative slack and negative slack from design compiler. But I don't know why do we need STA instead DC?
 
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Re: Why do we STA(Prime Time) after synthesis(Design compiler)?

DC is a synthesis tool and isn't really meant for timing. The timing report from DC isn't enough for a sign-off but only to make sure that the input for next stage in design flow is timing clean.

So an STA which is specifically for timing analysis must be used. The STA tool will do the sign-off check on the netlist got after the layout stage and report whether it is timing clean or not.

I suggest you read the book by Dr Hubert Kaeslin to get a good picture of the digital design flow. The book is very insightful on all the aspects of Digital design.
 

Re: Why do we STA(Prime Time) after synthesis(Design compiler)?

Thanks I have some question . Is this same meaning between negative slack and setup violation?
 

[Moved]Is this same thing positive skew and input clock delay?

Hi.

Is this same thing positive skew and input clock delay?
I am curious about how does the skew affect to setup and hold violation..
 
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Negative slack means there is a timing violation. It could be setup or hold depending on the timing you report.

I'm not sure what you mean by input clock delay. Skew means the clock arrives at different flip flops at different times, it can be positive or negative.

Positive skew has negative effect on hold timing and negative skew is bad while meeting setup time requirements. Once you draw a timing diagram you'll understand the reason better.

This article describes the concept of clock skew quite well.
 

Thanks Sir,

Does "negative slack" mean the same thing as setup violation? I'm confusing maximum delay meaning setup delay or minimum delay mean hold delay.

Especially, I am wondering about if Slack = Required time- Arrival time < 0 why this is setup violation?
 
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u24c02 said:
Thanks Sir,

Does "negative slack" mean the same thing as setup violation? I'm confusing maximum delay meaning setup delay or minimum delay mean hold delay.
Click to expand...


It doesn't necessarily. Imagine you ask the tool to report setup time for a particular path and it reports a negative slack, then that's setup violation. Same is applicable for hold time, or recovery and removal times as well for that matter.

As an engineer you always try to make sure that the design works at the worst possible conditions. So for setup time calculation always use the slow paths i.e. the maximum delay of the components to get the worst case timing.

For hold time calculation the fast paths will result in the worst case timing and hence use minimum delay of components.

Especially, I am wondering about if Slack = Required time- Arrival time < 0 why this is setup violation?
Click to expand...

Setup calculation :

Arrival time is the actual time taken by data to travel after it's launched by the launch flip flop to the D-input of the capture flop.

Required time is the time by which the data input is required to be stable before the capture clock active edge arrives.

So,
Required time = Clock period - Required setup time of capture flop
Arrival time = c2q of launch flop + propagation delay of logic between launch and capture flops.

Slack = Required time - Arrival time < 0 means data arrived late, thus leading to change of data in the setup window and causing a setup violation.

I have assumed clock network to be ideal here, hence no clock skew in the equation.
 

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