How common data bus is used internally in RAM chips

Status
Not open for further replies.
M

milan.rajik

Banned
Joined
Apr 1, 2013
Messages
2,524
Helped
540
Reputation
1,078
Reaction score
524
Trophy points
1,393
Visit site
Activity points
0
This is regarding to 8085 memory interfacing. In many books and other sources they mention that a RAM chip like 8K X 8 will have a CS pin connected to higher order address lines through address decoder circuit. A WR bar and RD bar lines which connect to Input tristate buffer and output tristate buffer. They also mention that there will be 8 input data lines to store data into RAM and 8 output data lines to read data from RAM but externally there will be only 8 bi-directional data bus. I want to know how the 8 input data lines and 8 output data lines are combined internally.
 

I want to know how the 8 input data lines and 8 output data lines are combined internally.
Click to expand...
hi,
Internally the 8051 Port pins are set by the program as Inputs or Outputs, depending upon whether its a Read or Write operation from the external memory.
Likewise the external memory IC will set its pins to Input or Output depending upon the WR & RD control pins set by the decoded program instruction, also CS is used to select a specific external IC.

Is this what you are asking.?
E
 
At least the question title is referring to internal design details of the SRAM.

It's quite easy to split a bidirectional bus into unidirectional busses by means of buffers, using the /RD or /OE line as tristate signal. In so far I don't see a specific problem with this operation. It's probably more interesting how the bus and address lines are translated to word and bit lines interfacing the elementary RAM 6-transistor cell.
 
I know how a tri-state buffer works but I have problem in understanding how a tri-state buffer works in this context (RAM interfacing). Can you provide a detailed block diagram on internal of RAM chip used for 8085 interfacing ? What happens if both /WR and /RD (/OE) lines are made low at the same time ? Tri states at input of RAM and output of RAM will be enabled ? what is the result? Will there be a circuit in side RAM chip to avoid this condition ?
 

Examples of internal RAM design can be found in digital IC design text books, I presume. It's also briefly answered in RAM datasheets. See e.g. this block diagram from a Hitachi HM6264. A datasheet also precisely answeres your specific question about /OE and /WE relation. Usually /WE takes precedence. A 8085 (or other processor) won't ever assert both signals simultaneously as far as I'm aware of. In so far it's a purely theoretical question.

 
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…