How can we implement PNP and NPN by CMOS in schemtaic

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bhl777

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Hi All, in some circuit applications, CMOS can be connected in some way to implement PNP and NPN. However, I only saw something in layout to implement these devices. Could anybody tell me, from the schematic wise, how can I connect G,S,D,B of PMOS and NMOS to make them work as parasitic PNP and NPN? Thank you!
 

The connection of parasitic BJTs in CMOS depends on the CMOS technology used. For standard CMOS processes (n-well in p-substrate) s. Fig. 5 on p. 3 of this Fairchild application note: View attachment Latchup-Reduction_in_CMOS.pdf
 
Hi erikl, thank you for posting this AN. I tried to understand it but am not familiar with this PNPN process. I use the drawing from Gray's book here and could you advise the following questions?

(1) Is my NPN connection correct? I connected GS together to disable both NMOS and PMOS.
(2) How can I choose a BASE of the PNP transistor in this picture?
(3）Can we use single MOS to implement single BJT? For example, can I use NMOS to implement NPN?
(4) Since we want to design the emitter area for BJT, is this relationship W X L (channel length and width of MOS channel)= Emitter area valid?
(5) If (4) is valid, does that mean we do not need to care about W/L, just WXL?

Thank you very much!


erikl said:
The connection of parasitic BJTs in CMOS depends on the CMOS technology used. For standard CMOS processes (n-well in p-substrate) s. Fig. 5 on p. 3 of this Fairchild application note: View attachment 102499
Click to expand...
 

You can tie the gate to the source (calling it now the
emitter) and drive the body terminal as the base, and
the drain is your collector. This will give you an easy,
low quality, barely- or poorly-modeled lateral BJT. And
it will carry a parasitci device or two along with it,
unless you're using an SOI technology.

Since the modeling is liable to be poor or nonexistent,
your circuit simulations are likely to work badly or not
at all. You may find yourself pulling curves and fitting
your own crude models. In that case it behooves you
to find, and stick to a geometry for a "unit cell" which
has the best BJT attributes (for example, a very wide
FET can make a poor BJT because base resistance
becomes high - despite that you would be driving the
excess "base" capacitance down by so doing). You
might look at circular / annular geometries for better
breakdown and high-Vce/Vcb behaviors that are
helped by controlling fields at "corner" features. But
then you will be even further afield (heh) when it
comes time for DRC/LVS.
 

bhl3302 said:
(1) Is my NPN connection correct?
Click to expand...
Yes, it is. But actually you always have 2 emitters: both source and drain. See this picture from a Rincón-Mora lecture, changed for n-well in p-substrate:


bhl3302 said:
(2) How can I choose a BASE of the PNP transistor in this picture?
Click to expand...
The n+ tap of the n-well. See your figure, with my additions in blue:


bhl3302 said:
(3）Can we use single MOS to implement single BJT? For example, can I use NMOS to implement NPN?
Click to expand...
Yes: just use the NMOS and an n-well (around, if possible), with the n+ tap as collector connection, as close as allowed by DRC.

If you are totally free in layout (apart from DRC rules) to design your own NPN, you could even use a single n+ implant for the emitter, a p+ implant as base connection around it, and an n+ in n-well as collector connection around - always clinging to DRC rules. Surely would create a better NPN. Some PDKs even offer such BJTs, with quite good simulation models.

bhl3302 said:
(4) Since we want to design the emitter area for BJT, is this relationship W X L (channel length and width of MOS channel)= Emitter area valid?
Click to expand...
No, it's the size of the source and drain implants.

bhl3302 said:
(5) If (4) is valid, does that mean we do not need to care about W/L, just WXL?
Click to expand...
Just use the source/drain implant size you need for the emitter area, and min. L.

But pls! note dick_freebird's comments! All these measures won't create good BJTs, they have rather low current gains (the NPNs probably < 10) at only limited collector currents, and not exactly low-noise.

You probably just get bad simulation models for these parasitic BJTs - may be none at all, so you would have to characterize them yourself.
 

Hi erikl, thank you for your advise! I am trying to understand this topic from theory, not for practical characterization. Regarding your answers, I still have couple questions, could you advise again?

(1) In your figure
for NPN, you connect G and S of MOS_G1 to emitter terminal, as you mentioned in my question 1. Am just wondering that what about G and S of MOS_G2? We can just leave them there with GS connected, without any other external connection?
(2) In your figure, for PNP, I am still confused about the equivalent Base terminal. It seems like you connect equivalent B with equivalent E? If so, how can this connection work like a PNP, once its B and E are shorted?
(3) regarding your answers to my original question 4 and 5, is the "a" in the following figure the implant size you mentioned? If so, can I say W x "a" is the emitter area of equivalent BJT?


Thank you!


 

No, you better connect it with the n-well bulk = collector .

bhl3302 said:
(2) In your figure, for PNP, I am still confused about the equivalent Base terminal. It seems like you connect equivalent B with equivalent E? If so, how can this connection work like a PNP, once its B and E are shorted?
Click to expand...
No, there's no connection; the base=bulk tap just crosses the (blue) S-G-D = emitter connection.

bhl3302 said:
(3) regarding your answers to my original question 4 and 5, is the "a" in the following figure the implant size you mentioned? If so, can I say W x "a" is the emitter area of equivalent BJT?
View attachment 103980
Click to expand...
No, a is the lateral width (not W of the PMOS) of the source & drain diffusions = emitter injection area.
 

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