How can we decrease clock skew?

[bharat_in]

How can we decrease clock skew?
i heard somtimes it is good to have in design, then why is that so, i mean how can it be helpful?

 

[sunjimmy]

clock-skew

It's better to balance the delay of colck-tree then the clock skew issue cab be relaxed. Many APR tools can do this for you after synthesis is done.

 

[mohdfayez]

Re: clock-skew

having clock skew helps in time budgeting in Partioned based design. where we can use the concept of something called as useful skew. if a design has some 4-5 then we can use the concept of useful skew to meet skew for the entire design.

 

[sohiltri]

Re: clock-skew

It depends on whether it is positive or negative skew.....

Both has it own advantage.....

With positive skew....It is useful as we can increase the freq of the clock ...
And negative skew does not effect much as long it is the multiples of clk time period....

 

[sowmya005]

Re: clock-skew

positive skew ---helps to meet the setup
negative skew---helps to meet the hold

 

[rkadarla]

Re: clock-skew

:arrow:

CTS : is the process where we try to minimise the skew in the design.
the clock skew can be minimised by the Post CTS optimization done by the tool, it resizes the clock buffers and the net lengths and balances the clock tree, most of these tools follow an algorithm which builds a binary tree for clock distribution.Binary tree can also be referred as Balanced H-tree.The skew that we are referring here is Local skew ( in one clock domain).

as the positive skew appears when the clock and the data flow in same directions,it helps in reducing the Tmax,hence actual Fmax can be Higher.( may raise race conditions)

as the negative skew appears when both the paths are in opposite directions, it increases the Tmax but unconditionally meets the hold conditions.

clock skew can also be minimised by manually editing ( make sure you use only clock buffer for optimisation) the nets when algorithm can't do it for any reason.

 

[pratap_v]

Re: clock-skew

this is very important in power consumption reduction because if clk skew is not zero than all the clocks would not reach all the flops at the same time and the drop(IR) is less.

 

[rkadarla]

Re: clock-skew

DROP (IR ) is less and do you think its more power consumption

 

[sohiltri]

Re: clock-skew

Please don bring power consumption topic into this discussion of clock skew...it isno way related....clock skew is something which happens naturally and dynamically....only we can do is to avoid negative effect due to it...u Cannot bring out adv from it because it is not in designer hands....

 

[phutanesv]

Re: clock-skew

Dear Dude,

Clock skew ocus due to mismath in load, mismatch in Rc dealy andin Process Varition.

So what we can do is to adjust the Slew rate of buffers to match the load.

else to alyer in net length so that RC delay ca match.

of course process varation is not in our hand.

Phutane

 

[smrjaved]

Re: clock-skew

Clock skew is of both positive and negative. It helps in designs when we have problems with set up and hold time violations. Positive skew helps in reducing set up time while negative skew helps in reducing the hold time violations. But it has to be used effectively using different techniques like reverse clocking strategies in case of negative skew.

 

[bharat_in]

Re: clock-skew

@smrjaved
what is reverse clocking strategy? Can you please, explain in a bit detail...

 

[phutanesv]

Re: clock-skew

Dear dude,

Reverse Clock staterging is making the clock in opposite to that of data, so that

the clock which has to reach nearest logic will take long path, and the clock which has to reach the longest path will take shortest path.

So that the clock skew can be adjusted or reduced.

This is one of the way to reduce clock skew.

phutane

 

[rajsrikanth]

Re: clock-skew

if u study any datasheet of fpga like spartan3 u can get the solution there to reduce the clock skew they explained how u can reduce or avoid clock skew.
we actually use delays

 

[vlsichipdesigner]

Re: clock-skew

dear Designer,

my 2 cents towards clock insertion/clock skew.

1. Number of Clock sinks
2. Balancing two different clock frequencies
3. Placement of clock sinks.
and to know more

Request you to visit this link to reduce the clock insertion/clock skew delay..
https://www.vlsichipdesign.com/steps_clock_insertion_reduction.html

Praise the Lord

best regards,
vlsichipdesigner
https://www.vlsichipdesign.com
[ASIC Chip Design for Free]

 

[cihchenlin]

Re: clock-skew

i learn more,thanks