Jul 5, 2015 #1 F fahim1 Member level 4 Joined Jun 4, 2015 Messages 75 Helped 2 Reputation 4 Reaction score 2 Trophy points 8 Activity points 517 Hi I want to use a component inside my code with the clock that is 1/8 of the clock of main code, how should i declare it in the portmap?
Hi I want to use a component inside my code with the clock that is 1/8 of the clock of main code, how should i declare it in the portmap?
Jul 5, 2015 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 You should create a clock enable (, and run the component at the full clock rate. Using divided clocks will cause you all sorts of problems later on. example, clock enable that runs at 1/8th the main clock: Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 signal clk_en_div_8 : std_logic; signal div_cnt : unsigned(2 downto 0) := "000"; process(clk) begin if rising_edge(clk) then div_cnt <= div_cnt + 1; if div_cnt = 0 then clk_en_div_8 <= '1'; else clk_en_div_8 <= '0'; end if; end if; end process; then inside your component, passing the clock enable through the port map: Code VHDL - [expand]1 2 3 4 5 6 7 8 process(clk) begin if rising_edge(clk) then if clk_en_div_8 = '1' then --code here runs at 1/8 clock speed end if; end if; end process; All good text books and tutorials should teach this as a basic step - does yours not teach you these things?
You should create a clock enable (, and run the component at the full clock rate. Using divided clocks will cause you all sorts of problems later on. example, clock enable that runs at 1/8th the main clock: Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 signal clk_en_div_8 : std_logic; signal div_cnt : unsigned(2 downto 0) := "000"; process(clk) begin if rising_edge(clk) then div_cnt <= div_cnt + 1; if div_cnt = 0 then clk_en_div_8 <= '1'; else clk_en_div_8 <= '0'; end if; end if; end process; then inside your component, passing the clock enable through the port map: Code VHDL - [expand]1 2 3 4 5 6 7 8 process(clk) begin if rising_edge(clk) then if clk_en_div_8 = '1' then --code here runs at 1/8 clock speed end if; end if; end process; All good text books and tutorials should teach this as a basic step - does yours not teach you these things?