newbie_1
Member level 3
hi, i have a question about verilog,
how can i convert the following code using assign?
always @(*)
begin
case(d1)
2'b000: begin
do1 = 3'b101;
do2 = 3'b110;
end
2'b001: begin
do1 = 3'b101;
do2 = 3'b111;
end
2'b010: begin
....
....
2'b111: begin
do1 = 3'b001;
do2 = 3'b010;
default: begin
do1 = 3'b000;
do2 = 3'b000;
end
endcase
end
i don't wanna use the always sentence, and how can i rewrite the above code very briefly and make the code easy to be read?
thanks a lot
how can i convert the following code using assign?
always @(*)
begin
case(d1)
2'b000: begin
do1 = 3'b101;
do2 = 3'b110;
end
2'b001: begin
do1 = 3'b101;
do2 = 3'b111;
end
2'b010: begin
....
....
2'b111: begin
do1 = 3'b001;
do2 = 3'b010;
default: begin
do1 = 3'b000;
do2 = 3'b000;
end
endcase
end
i don't wanna use the always sentence, and how can i rewrite the above code very briefly and make the code easy to be read?
thanks a lot