how can this code be rewrite using "assign"?

[newbie_1]

hi, i have a question about verilog,
how can i convert the following code using assign?

always @(*)
begin
case(d1)
2'b000: begin
do1 = 3'b101;
do2 = 3'b110;
end
2'b001: begin
do1 = 3'b101;
do2 = 3'b111;
end
2'b010: begin
....
....
2'b111: begin
do1 = 3'b001;
do2 = 3'b010;
default: begin
do1 = 3'b000;
do2 = 3'b000;
end
endcase
end


i don't wanna use the always sentence, and how can i rewrite the above code very briefly and make the code easy to be read?


thanks a lot

 

[sbob]

Hint: make a mux for do1 and do2.

assign do1[2:0] = (d1[2:0] == 3'b000) ? 3'b101 :
(d1[2:0] == 3'b001) ? 3'b101:
...

 

[luxboy]

How about synthesis and convert back? Only idea, but I don't know how to implement

 

[arsenal]

it will be very tedious if u use assign ,
try still using case statement, and add d1 to the sensitivity list,
it will be ok to be synthesized